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    Pipe
    4.
    发明授权
    Pipe 有权

    公开(公告)号：US10107421B2

    公开(公告)日：2018-10-23

    申请号：US13983598

    申请日：2012-02-07

    申请人： Alan Wood ,  Horst Sandner

    发明人： Alan Wood ,  Horst Sandner

    IPC分类号： F16L9/12 ,  B29C71/00 ,  C08J5/00 ,  F16L11/06 ,  E21B17/01 ,  B29C47/00 ,  B29C47/90 ,  B29C71/02 ,  B29K71/00 ,  B29C47/88

    摘要： A polyetheretherketone pipe of length greater than 250 meters and a residual stress of less than 5 MPa may be made using a calibrator device (2) which includes a cone shaped opening (6) arranged to receive a molten extruded pipe shaped polymer. Attached to the front member (4) is a vacuum plate (14a) and successive vacuum plates (14b-14h) are attached to one another to define an array of vacuum plates, the vacuum plates being arranged to allow a vacuum to be applied to a pipe precursor passing through opening (16). The vacuum plates (14) also include (10) temperature control means for heating or cooling the plates and therefore heating or cooling a pipe precursor passing through the openings. With a vacuum applied to opening (6, 16) and heating/cooling the plates, an extruded hot plastics pipe is inserted into calibrator (2) via opening (6) and conveyed through opening (16) in plates (14), whereupon it is urged by the vacuum against the cylindrical surface defined by plates (14) to maintain its shape and the (15) temperature of each plate is controlled to control the rate of cooling of the pipe precursor passing through. The pipe may be cooled at a relatively slow rate so that a pipe made from a relatively fast crystallizing polymer crystallizes and the crystallinity of the pipe along its extent and throughout its thickness is substantially constant.

    PIPE
    6.
    发明申请
    PIPE 审中-公开
    管

    公开(公告)号：US20130306188A1

    公开(公告)日：2013-11-21

    申请号：US13983598

    申请日：2012-02-07

    申请人： Alan Wood ,  Horst Sandner

    发明人： Alan Wood ,  Horst Sandner

    IPC分类号： F16L9/12

    CPC分类号： F16L9/12 ,  B29C47/0023 ,  B29C47/0092 ,  B29C47/8835 ,  B29C47/884 ,  B29C47/8865 ,  B29C47/903 ,  B29C47/904 ,  B29C71/0063 ,  B29C71/02 ,  B29C2791/006 ,  B29K2071/00 ,  C08J5/00 ,  C08J2371/10 ,  C08J2381/02 ,  E21B17/01 ,  F16L11/06

    摘要： A polyetheretherketone pipe of length greater than 250 meters and a residual stress of less than 5 MPa may be made using a calibrator device (2) which includes a cone shaped opening (6) arranged to receive a molten extruded pipe shaped polymer. Attached to the front member (4) is a vacuum plate (14a) and successive vacuum plates (14b-14h) are attached to one another to define an array of vacuum plates, the vacuum plates being arranged to allow a vacuum to be applied to a pipe precursor passing through opening (16). The vacuum plates (14) also include (10) temperature control means for heating or cooling the plates and therefore heating or cooling a pipe precursor passing through the openings. With a vacuum applied to opening (6, 16) and heating/cooling the plates, an extruded hot plastics pipe is inserted into calibrator (2) via opening (6) and conveyed through opening (16) in plates (14), whereupon it is urged by the vacuum against the cylindrical surface defined by plates (14) to maintain its shape and the (15) temperature of each plate is controlled to control the rate of cooling of the pipe precursor passing through. The pipe may be cooled at a relatively slow rate so that a pipe made from a relatively fast crystallising polymer crystalises and the crystallinity of the pipe along its extent and throughout its thickness is substantially constant.

    摘要翻译： 长度大于250米，残余应力小于5MPa的聚醚醚酮管可以使用校准器装置（2）制成，所述校准装置包括设置成容纳熔融挤出管状聚合物的锥形开口（6）。 附接到前部构件（4）的是真空板（14a），并且连续的真空板（14b-14h）彼此附接以限定真空板阵列，真空板被布置成允许将真空施加到 通过开口（16）的管前体。 真空板（14）还包括（10）用于加热或冷却板的温度控制装置，因此加热或冷却通过开口的管状母体。 通过将真空施加到开口（6,16）并加热/冷却板，将挤出的热塑料管通过开口（6）插入到校准器（2）中，并通过板（14）中的开口（16）输送， 被真空推压到由板（14）限定的圆柱形表面上以保持其形状，并且控制每个板的（15）温度以控制通过的管前体的冷却速率。 管可以以相对较慢的速率冷却，使得由相对快速的结晶聚合物制成的管结晶，并且管的结晶度沿着其程度并且整个厚度基本上恒定。

    UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN
    8.
    发明申请
    UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN 失效
    通用水平滚轮加速器

    公开(公告)号：US20070285115A1

    公开(公告)日：2007-12-13

    申请号：US11841566

    申请日：2007-08-20

    申请人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

    发明人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

    IPC分类号： G01R31/02 ,  G01R1/06

    CPC分类号： G01R31/2863

    摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

    摘要翻译： 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

    Methods for fabricating and filling conductive vias and conductive vias so formed
    9.
    发明申请
    Methods for fabricating and filling conductive vias and conductive vias so formed 有权
    制造和填充如此形成的导电通孔和导电通孔的方法

    公开(公告)号：US20070184654A1

    公开(公告)日：2007-08-09

    申请号：US11347153

    申请日：2006-02-03

    申请人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    发明人： Salman Akram ,  William Hiatt ,  Steve Oliver ,  Alan Wood ,  Sidney Rigg ,  James Wark ,  Kyle Kirby

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

    摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

    摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其他特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。