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1.发明授权Method and system for a semiconductor device package with a die to interposer wafer first bond 有权一种半导体器件封装的方法和系统，其具有管芯至插入件晶片第一接合公开(公告)号：US09040349B2
公开(公告)日：2015-05-26
申请号：US13678046
申请日：2012-11-15
IPC分类号： H01L21/50
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/50 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/49805 , H01L23/49816 , H01L23/49838 , H01L23/5384 , H01L24/13 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L27/108 , H01L2221/68381 , H01L2224/13147 , H01L2224/29011 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/75704 , H01L2224/75744 , H01L2224/7598 , H01L2224/81005 , H01L2224/8114 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83192 , H01L2224/83203 , H01L2224/83862 , H01L2224/9211 , H01L2224/97 , H01L2924/12042 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.
摘要翻译： 公开了具有管芯到插入件晶片第一接合的半导体器件封装的方法和系统，并且可以包括将包括电子器件的多个半导体管芯结合到插入器晶片，以及在管芯和插入器晶片之间施加底部填充材料。 可以应用模具材料来封装模具。 内插器晶片可以被薄化以暴露通过硅通孔（TSV），并且可以将金属触点施加到暴露的TSV。 内插器晶片可以被单个化以产生包括半导体管芯和插入器管芯的组件。 可以使用粘合剂膜将管芯放置在插入件晶片上。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器晶片。 可以使用质量回流或热压缩工艺将管芯结合到插入件晶片。
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2.发明申请Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond 有权用于器件封装的半导体的方法和系统具有封装到封装的基板第一键公开(公告)号：US20140134804A1
公开(公告)日：2014-05-15
申请号：US13678058
申请日：2012-11-15
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/50 , H01L21/563 , H01L21/67288 , H01L21/6836 , H01L21/6838 , H01L21/68735 , H01L23/147 , H01L23/3107 , H01L23/3128 , H01L23/3142 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5386 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68322 , H01L2223/54486 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/27622 , H01L2224/2763 , H01L2224/29011 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83101 , H01L2224/83104 , H01L2224/83192 , H01L2224/83203 , H01L2224/83855 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/16235 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/81
摘要： Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. The additional die may comprise electronic devices. The first semiconductor die may comprise an interposer die or may comprise electronic devices. The first semiconductor die may be bonded to the packaging substrate utilizing a mass reflow process or a thermal compression process. The additional die may be bonded to the first die utilizing a mass reflow process or a thermal compression process. The bonded die may be encapsulated in a mold material, which may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the first semiconductor die.
摘要翻译： 公开了具有管芯到基板的第一接合的半导体器件封装的方法和系统，并且可以包括将第一半导体管芯接合到封装基板，在第一半导体管芯和封装基板之间施加底部填充材料， 或更多的额外管芯到第一半导体管芯。 附加的管芯可以包括电子器件。 第一半导体管芯可以包括插入器管芯，或者可以包括电子器件。 第一半导体管芯可以利用质量回流工艺或热压缩工艺结合到封装衬底上。 可以使用质量回流工艺或热压缩工艺将附加模具结合到第一模具。 粘合的模具可以包封在可以包含聚合物的模具材料中。 一个或多个附加管芯可以包括用于耦合到第一半导体管芯的微突起。
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3.发明申请Method And System For A Semiconductor Device Package With A Die-To-Die First Bond 有权一种具有芯片到芯片第一键的半导体器件封装的方法和系统公开(公告)号：US20140134803A1
公开(公告)日：2014-05-15
申请号：US13678012
申请日：2012-11-15
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6838 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L25/0652 , H01L25/0655 , H01L2224/13147 , H01L2224/13564 , H01L2224/16147 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/75705 , H01L2224/75744 , H01L2224/81011 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83001 , H01L2224/83192 , H01L2224/83851 , H01L2224/83855 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2924/0781 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2224/16225 , H01L2924/00 , H01L2224/16145
摘要： Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.
摘要翻译： 公开了具有管芯到管芯第一接合的半导体器件封装的方法，并且可以包括将包括电子器件的一个或多个半导体管芯接合到插入器管芯。 可以在半导体管芯和内插管芯之间施加底部填充材料，并且可以施加模具材料以封装半导体管芯。 内插器管芯可以变薄以暴露通过硅通孔（TSV）。 半导体管芯的接合可以包括将半导体管芯粘附到粘合剂层上，并将半导体管芯接合到插入器管芯。 半导体管芯可以包括用于耦合到插入式管芯的微型突起，其中，所述接合包括：将微型凸块定位在设置在所述插入式管芯上的层中的相应的阱中; 并将微型凸块接合到插入件模具。 半导体管芯可以利用质量回流工艺或热压缩工艺结合到插入式管芯上。
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4.发明授权Method and system for a semiconductor for device package with a die-to-packaging substrate first bond 有权用于具有管芯到封装衬底第一接合的器件封装的半导体的方法和系统公开(公告)号：US09136159B2
公开(公告)日：2015-09-15
申请号：US13678058
申请日：2012-11-15
IPC分类号： H01L21/762 , H01L23/14 , H01L21/48 , H01L21/683 , H01L23/544 , H01L23/00 , H01L23/498
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/50 , H01L21/563 , H01L21/67288 , H01L21/6836 , H01L21/6838 , H01L21/68735 , H01L23/147 , H01L23/3107 , H01L23/3128 , H01L23/3142 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5386 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68322 , H01L2223/54486 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/27622 , H01L2224/2763 , H01L2224/29011 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83101 , H01L2224/83104 , H01L2224/83192 , H01L2224/83203 , H01L2224/83855 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/16235 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/81
摘要： Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. The additional die may comprise electronic devices. The first semiconductor die may comprise an interposer die or may comprise electronic devices. The first semiconductor die may be bonded to the packaging substrate utilizing a mass reflow process or a thermal compression process. The additional die may be bonded to the first die utilizing a mass reflow process or a thermal compression process. The bonded die may be encapsulated in a mold material, which may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the first semiconductor die.
摘要翻译： 公开了具有管芯到基板的第一接合的半导体器件封装的方法和系统，并且可以包括将第一半导体管芯接合到封装基板，在第一半导体管芯和封装基板之间施加底部填充材料， 或更多的额外管芯到第一半导体管芯。 附加的管芯可以包括电子器件。 第一半导体管芯可以包括插入器管芯，或者可以包括电子器件。 第一半导体管芯可以利用质量回流工艺或热压缩工艺结合到封装衬底上。 可以使用质量回流工艺或热压缩工艺将附加模具结合到第一模具。 粘合的模具可以包封在可以包含聚合物的模具材料中。 一个或多个附加管芯可以包括用于耦合到第一半导体管芯的微突起。
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5.发明授权Method and system for a semiconductor device package with a die-to-die first bond 有权具有管芯到管芯第一接合的半导体器件封装的方法和系统公开(公告)号：US08796072B2
公开(公告)日：2014-08-05
申请号：US13678012
申请日：2012-11-15
IPC分类号： H01L21/00
CPC分类号： H01L21/76251 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6838 , H01L23/147 , H01L23/3128 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L25/0652 , H01L25/0655 , H01L2224/13147 , H01L2224/13564 , H01L2224/16147 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/75705 , H01L2224/75744 , H01L2224/81011 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83001 , H01L2224/83192 , H01L2224/83851 , H01L2224/83855 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2924/0781 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/3511 , H01L2924/00014 , H01L2224/16225 , H01L2924/00 , H01L2224/16145
摘要： Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.
摘要翻译： 公开了具有管芯到管芯第一接合的半导体器件封装的方法，并且可以包括将包括电子器件的一个或多个半导体管芯接合到插入器管芯。 可以在半导体管芯和内插管芯之间施加底部填充材料，并且可以施加模具材料以封装半导体管芯。 内插器管芯可以变薄以暴露通过硅通孔（TSV）。 半导体管芯的接合可以包括将半导体管芯粘附到粘合剂层上，并将半导体管芯接合到插入器管芯。 半导体管芯可以包括用于耦合到插入式管芯的微型突起，其中，所述接合包括：将微型凸块定位在设置在所述插入式管芯上的层中的相应的阱中; 并将微型凸块接合到插入件模具。 半导体管芯可以利用质量回流工艺或热压缩工艺结合到插入式管芯上。
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6.发明申请Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond 有权一种半导体器件封装的方法和系统，具有内插器晶片第一键公开(公告)号：US20140134796A1
公开(公告)日：2014-05-15
申请号：US13678046
申请日：2012-11-15
IPC分类号： H01L21/50
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/50 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/49805 , H01L23/49816 , H01L23/49838 , H01L23/5384 , H01L24/13 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L27/108 , H01L2221/68381 , H01L2224/13147 , H01L2224/29011 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/75704 , H01L2224/75744 , H01L2224/7598 , H01L2224/81005 , H01L2224/8114 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83192 , H01L2224/83203 , H01L2224/83862 , H01L2224/9211 , H01L2224/97 , H01L2924/12042 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.
摘要翻译： 公开了具有管芯到插入件晶片第一接合的半导体器件封装的方法和系统，并且可以包括将包括电子器件的多个半导体管芯结合到插入器晶片，以及在管芯和插入器晶片之间施加底部填充材料。 可以应用模具材料来封装模具。 内插器晶片可以被薄化以暴露通过硅通孔（TSV），并且可以将金属触点施加到暴露的TSV。 内插器晶片可以被单个化以产生包括半导体管芯和插入器管芯的组件。 可以使用粘合剂膜将管芯放置在插入件晶片上。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器晶片。 可以使用质量回流或热压缩工艺将管芯结合到插入件晶片。
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7.发明授权Method and system for backside dielectric patterning for wafer warpage and stress control 有权用于晶片翘曲和应力控制的背面电介质图案化方法和系统公开(公告)号：US08987050B1
公开(公告)日：2015-03-24
申请号：US13690817
申请日：2012-11-30
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/312 , H01L21/31 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/31 , H01L21/312 , H01L21/486 , H01L21/50 , H01L21/6835 , H01L23/147 , H01L23/3171 , H01L23/3192 , H01L23/3675 , H01L23/48 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/6834 , H01L2221/68345 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1421 , H01L2924/1433 , H01L2924/14335 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/1616 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/11 , H01L2224/03
摘要： Methods and systems for backside dielectric patterning for wafer warpage and stress control are disclosed and may include thinning a semiconductor wafer comprising one or more through silicon vias (TSVs) and one or more die to expose the TSVs on a first surface of the wafer. The wafer may be passivated by depositing dielectric layers. The passivated wafer may be planarized and portions dielectric layers may be selectively removed to reduce a strain on the wafer. Metal contacts may be placed on the exposed TSVs prior to or after the selectively removal. The die may comprise functional electronic die or interposer die. Portions of the dielectric layers may be selectively removed in a radial pattern and may comprise a nitride and/or silicon dioxide layer. The wafer may be thinned to below a top surface of the TSVs. The dielectric layers may be selectively removed utilizing a dry etch process.
摘要翻译： 公开了用于晶片翘曲和应力控制的背面电介质图案化的方法和系统，并且可以包括使包括一个或多个通孔（TSV）和一个或多个管芯的半导体晶片变薄以暴露晶片的第一表面上的TSV。 可以通过沉积介电层来钝化晶片。 钝化的晶片可以被平坦化，并且可以选择性地去除部分电介质层以减小晶片上的应变。 可以在选择性移除之前或之后将金属触点放置在暴露的TSV上。 芯片可以包括功能电子管芯或插入件管芯。 可以以径向图案选择性地去除介电层的一部分，并且可以包括氮化物和/或二氧化硅层。 晶片可以变薄到TSV的顶表面之下。 可以使用干蚀刻工艺来选择性地去除电介质层。
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公开(公告)号：US08802499B2
公开(公告)日：2014-08-12
申请号：US13678026
申请日：2012-11-15
IPC分类号： H01L21/00
CPC分类号： H01L21/486 , H01L21/56 , H01L21/561 , H01L21/568 , H01L22/14 , H01L22/20 , H01L23/04 , H01L23/147 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81191 , H01L2224/81908 , H01L2224/81986 , H01L2224/83192 , H01L2224/83908 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/00
摘要： Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.
摘要翻译： 用于片上晶片组装的临时晶片成型的方法可以包括将一个或多个半导体管芯接合到插入器晶片，施加临时模制材料以封装接合的管芯，以及背面处理插入件，其可以被单个化以产生组件， 可以粘合到封装衬底上的粘合模，插入模。 可以移除临时模具材料并且可以测试粘合的模具。 基于电气测试，附加模具可以结合到组件。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器。 背面处理可以包括使内插器晶片变薄以暴露穿过硅通孔（TSV）并且将金属触点放置在暴露的TSV上。 可以使用质量回流或热压缩工艺将管芯结合到插入件。
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公开(公告)号：US08390130B1
公开(公告)日：2013-03-05
申请号：US12985888
申请日：2011-01-06
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/6836 , H01L23/481 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2224/73204 , H01L2224/81141 , H01L2224/81191 , H01L2224/81203 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06593 , H01L2924/00014 , H01L2924/10158 , H01L2224/81 , H01L2924/014 , H01L2224/05552
摘要： A stacked assembly includes a stacked structure stacked on a through via recessed reveal structure. The through via recessed reveal structure includes recesses within a backside surface of an electronic component that expose backsides of through vias. Pillars of the stacked structure are attached to the exposed backsides of the through vias through the recesses. The recesses in combination with the pillars work as a lock and key arrangement to insure self-alignment of the pillars with the backsides of the through vias allowing fine pitch interconnections to be realized. Further, by forming the interconnections to the backsides of the through vias within the recesses, the overall thickness of the stacked assembly is minimized. Further still, by forming the interconnections to the backsides of the through vias within the recesses, shorting between adjacent through vias is minimized or eliminated.
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公开(公告)号：US20140134800A1
公开(公告)日：2014-05-15
申请号：US13678026
申请日：2012-11-15
IPC分类号： H01L21/78 , H01L21/762
CPC分类号： H01L21/486 , H01L21/56 , H01L21/561 , H01L21/568 , H01L22/14 , H01L22/20 , H01L23/04 , H01L23/147 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2224/73253 , H01L2224/81001 , H01L2224/81191 , H01L2224/81908 , H01L2224/81986 , H01L2224/83192 , H01L2224/83908 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/16152 , H01L2924/1616 , H01L2924/18161 , H01L2924/19105 , H01L2924/00
摘要： Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.
摘要翻译： 用于片上晶片组装的临时晶片成型的方法可以包括将一个或多个半导体管芯接合到插入器晶片，施加临时模制材料以封装接合的管芯，以及背面处理插入件，其可以被单个化以产生组件， 可以粘合到封装衬底上的粘合模，插入模。 可以移除临时模具材料并且可以测试粘合的模具。 基于电气测试，附加模具可以结合到组件。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器。 背面处理可以包括使内插器晶片变薄以暴露穿过硅通孔（TSV）并将金属触点放置在暴露的TSV上。 可以使用质量回流或热压缩工艺将管芯结合到插入件。
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