公开(公告)号：US10231324B2

公开(公告)日：2019-03-12

申请号：US14264836

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

IPC: H01L21/48 ,  H05K1/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L23/522 ,  H01L23/525

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

公开(公告)号：US09514966B2

公开(公告)日：2016-12-06

申请号：US14251236

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01L23/58 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01R13/6471

CPC classification number: H01L21/4885 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01R13/6471

Abstract: The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Abstract translation: 本公开涉及半导体封装中的引脚布局。 本公开的一个实施例提供了一种隔离一组差分引脚对的菱形共享参考引脚布局。 差分信号引脚对被配置为使得由垂直信号引脚对形成的轴线与横向信号引脚对形成的轴线正交并相互平分。

公开(公告)号：US11784157B2

公开(公告)日：2023-10-10

申请号：US17339830

申请日：2021-06-04

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Charles David Paynter ,  Ryan Lane ,  Jianwen Xu ,  William Stone

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17163 ,  H01L2224/2105 ,  H01L2224/24145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US10321575B2

公开(公告)日：2019-06-11

申请号：US14842403

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane ,  Ruey Kae Zang

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H01L23/64 ,  H01L21/48 ,  H01L23/13 ,  H01L23/16

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

公开(公告)号：US09871012B2

公开(公告)日：2018-01-16

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

公开(公告)号：US20150279545A1

公开(公告)日：2015-10-01

申请号：US14229367

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F27/28 ,  H01F27/29 ,  H01F27/24

CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括芯层，第一通孔，第一介电层和第一电感器的封装衬底。 芯层包括第一表面和第二表面。 第一个通孔位于核心层。 第一介电层耦合到芯层的第一表面。 第一电感器位于第一电介质层中。 第一电感器耦合到芯层中的第一通孔。 第一电感器被配置为产生横向穿过封装衬底的磁场。 在一些实施方案中，封装衬底还包括耦合到第一电感器的第一焊盘，其中第一焊盘被配置为耦合到焊球。 在一些实施方案中，封装衬底包括位于芯层中的第二通孔和位于第一介电层中的第二电感器。

公开(公告)号：US20240107665A1

公开(公告)日：2024-03-28

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10015 ,  H05K2201/10734

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

公开(公告)号：US10008316B2

公开(公告)日：2018-06-26

申请号：US14229367

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01L23/498 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

公开(公告)号：US20150206854A1

公开(公告)日：2015-07-23

申请号：US14268974

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Charles David Paynter ,  David Ian West

IPC: H01L25/065 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Abstract translation: 一些特征涉及包括第一封装，一组互连和第二封装的集成器件。 第一包装包括包括第一表面和第二表面的第一基底。 第一包装包括重分配部分，其包括再分配层。 第一封装包括耦合到第一衬底的第一表面的第一裸片。 该组互连耦合到第一封装的再分配部分。 第二包通过一组互连耦合到第一包装。 第二包装包括包括第一表面和第二表面的第二基底; 以及第二管芯，其耦合到所述第二衬底的所述第一表面，其中所述第二管芯通过所述第二封装的所述第二衬底，所述一组互连和所述第一封装的再分配部分电耦合到所述第一管芯。

公开(公告)号：US20140061642A1

公开(公告)日：2014-03-06

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract translation: 这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。 该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。 外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。 在所公开的方法的各个方面，外部互连由模具的包装保护。