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    PORTABLE TERMINAL AND METHOD OF CONTROLLING THEREOF
    2.
    发明申请
    PORTABLE TERMINAL AND METHOD OF CONTROLLING THEREOF 审中-公开
    便携式终端及其控制方法

    公开(公告)号：US20160196760A1

    公开(公告)日：2016-07-07

    申请号：US14985666

    申请日：2015-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gyo-Seung KOO ,  Dong-Hun PARK ,  Hee-Jae JUNG ,  Jung-Hwan KIM ,  Ji-Ho MA ,  Ae-Seon SEO ,  Jung-Ho SEO

    IPC: G09B5/02 ,  G09B19/00

    CPC classification number: G09B5/02 ,  G09B19/0038

    Abstract: Disclosed herein are a portable terminal and method. The portable terminal includes a display module and at least one processor operatively coupled to the memory, which may implemented the method to control the display module to display a first image operable to indicate a state of a user, and in response to receiving response information while the first image is displayed, determine a state of the user according to the received response information.

    Abstract translation: 这里公开了便携式终端和方法。 便携式终端包括显示模块和可操作地耦合到存储器的至少一个处理器，其可以实现控制显示模块的方法来显示可操作以指示用户的状态的第一图像，并且响应于接收到响应信息， 显示第一图像，根据接收的响应信息确定用户的状态。

    INITIATOR AND METHOD FOR DEBONDING WAFER SUPPORTING SYSTEM
    5.
    发明申请
    INITIATOR AND METHOD FOR DEBONDING WAFER SUPPORTING SYSTEM 有权
    阻尼支撑系统的起动器和方法

    公开(公告)号：US20160093518A1

    公开(公告)日：2016-03-31

    申请号：US14788783

    申请日：2015-06-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu-Dong JUNG ,  Jung-Hwan KIM ,  Dong-Gil LEE ,  Tae-Je CHO ,  Kwang-Chul CHOI

    IPC: H01L21/67 ,  B32B43/00

    CPC classification number: H01L21/67115 ,  B32B38/10 ,  B32B41/00 ,  B32B43/006 ,  B32B2250/02 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67253 ,  H01L2221/68381 ,  H01L2224/98 ,  Y10T156/1158 ,  Y10T156/1917

    Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

    Abstract translation: 提供了一种用于剥离晶片支撑系统的引发剂和方法。 用于剥离晶片支撑系统的启动器包括具有上表面的旋转卡盘，其上包括载体晶片的晶片支撑系统（WSS），器件晶片和用于将载体晶片和器件晶片接合的胶层 彼此坐下来旋转晶片支撑系统，检测模块检测胶层的高度和厚度;以及激光模块，其通过用激光照射胶层的侧表面而在胶层上产生断裂部分 胶层的高度和厚度的基础。

    METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140106537A1

    公开(公告)日：2014-04-17

    申请号：US14053913

    申请日：2013-10-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  HungSuk KIM ,  Guk-Hyon YON ,  Hunhyeong LIM

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

    Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220384482A1

    公开(公告)日：2022-12-01

    申请号：US17881707

    申请日：2022-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  Dongkyum KIM ,  Seulye KIM ,  Ji-Hoon CHOI

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/04 ,  H01L29/423 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220115294A1

    公开(公告)日：2022-04-14

    申请号：US17331951

    申请日：2021-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil KIM ,  Jinhyuk KIM ,  Jung-Hwan KIM

    IPC: H01L23/48 ,  H01L29/78 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065

    Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

    VERTICAL MEMORY DEVICES
    10.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20210217771A1

    公开(公告)日：2021-07-15

    申请号：US17195756

    申请日：2021-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Hoon CHOI ,  Sung-Gil KIM ,  Jung-Hwan KIM ,  Chan-Hyoung KIM ,  Woo-Sung LEE

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

    Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

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