公开(公告)号：US08623743B2

公开(公告)日：2014-01-07

申请号：US13741466

申请日：2013-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Do Lee ,  JongKook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。

公开(公告)号：US11133296B2

公开(公告)日：2021-09-28

申请号：US16698749

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanhee Jeong ,  Hyunki Kim ,  Junwoo Park ,  Byoung Wook Jang ,  Sunchul Kim ,  Su-Min Park ,  Pyoungwan Kim ,  Inku Kang ,  Heeyeol Kim

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

公开(公告)号：US10593652B2

公开(公告)日：2020-03-17

申请号：US16448392

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00 ,  H01L23/48

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US10403606B2

公开(公告)日：2019-09-03

申请号：US15971600

申请日：2018-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48

Abstract: A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.

公开(公告)号：US20190319012A1

公开(公告)日：2019-10-17

申请号：US16448392

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu KWON ,  Min-Ok NA ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/10 ,  H01L23/552 ,  H01L23/498 ,  H01L25/00

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US09978721B2

公开(公告)日：2018-05-22

申请号：US15241452

申请日：2016-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H05K1/11 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01064 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US09837272B2

公开(公告)日：2017-12-05

申请号：US15092263

申请日：2016-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Min Park ,  Su-Min Kim ,  Hyo-Jin Yun ,  Hyun-Woo Kim ,  Kyoung-Seon Kim ,  Hai-Sub Na ,  Min-Ju Park ,  So-Ra Han

IPC: H01L21/302 ,  H01L21/461 ,  H01B13/00 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L21/033 ,  H01L21/322 ,  H01L21/426 ,  H01L21/425 ,  H01L21/311 ,  H01L27/108

CPC classification number: H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3223 ,  H01L21/425 ,  H01L21/426 ,  H01L27/10855 ,  H01L27/10888

Abstract: In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.

公开(公告)号：US20130130472A1

公开(公告)日：2013-05-23

申请号：US13741466

申请日：2013-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Do LEE ,  Jongkook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。