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    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20230079686A1

    公开(公告)日：2023-03-16

    申请号：US17717619

    申请日：2022-04-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Hun CHEONG ,  Young Lyong KIM ,  Cheol Soo HAN

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

    Abstract: Provided is a semiconductor package with improved reliability. The semiconductor package includes: a plurality of connection terminals on a first surface of the semiconductor device; a protection member on the first surface of the semiconductor device and partially covers side surfaces of the plurality of connection terminals such that the protective member exposes lower surfaces of the plurality of connection terminals; and a mold member that covers a side surface of the semiconductor device and a portion of the protection member such that the mold member does not cover the lower surfaces of the plurality of connection terminals.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220020656A1

    公开(公告)日：2022-01-20

    申请号：US17185116

    申请日：2021-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon JUNG ,  Young Lyong KIM ,  Cheolsoo HAN

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

    Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

    SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS
    5.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS 有权

    公开(公告)号：US20250046745A1

    公开(公告)日：2025-02-06

    申请号：US18595216

    申请日：2024-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young Lyong KIM

    IPC: H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor package includes first and second chips horizontally spaced apart from each other on a substrate. An under-fill layer is interposed between the substrate and the first and second chips. An upper mold layer is disposed on the substrate to cover side surfaces of the first and second chips. The second chip includes vertically-stacked sub-chips and a chip mold layer covering side surfaces of the sub-chips. The under-fill layer extends into a space between lower side surfaces of the chip mold layer and the first chip. The upper mold layer extends into a space between upper side surfaces of the chip mold layer and the first chip to cover an uppermost surface of the under-fill layer. The upper side surface of the chip mold layer is recessed inward from the lower side surface of the chip mold layer.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210183821A1

    公开(公告)日：2021-06-17

    申请号：US17183786

    申请日：2021-02-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyeong KIM ,  Young Lyong KIM ,  Geol NAM

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

    Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

    SEMICONDUCTOR PACKAGE
    10.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190013272A1

    公开(公告)日：2019-01-10

    申请号：US15870910

    申请日：2018-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geol NAM ,  Young Lyong KIM

    IPC: H01L23/538 ,  H01L25/065

    CPC classification number: H01L23/5385 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544

    Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.

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