公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09257393B1

公开(公告)日：2016-02-09

申请号：US14500698

申请日：2014-09-29

申请人： Zhiwei Gong ,  Weng F. Yap

发明人： Zhiwei Gong ,  Weng F. Yap

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC分类号： H01L23/3114 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/78 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/29147 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

摘要翻译： 提供扇出晶圆级封装（FO-WLP）和制造包含嵌入式地平线（EGP）和背面EGP互连结构的FO-WLP的方法。 在一个实施例中，该方法包括通过背面EGP互连结构将EGP电耦合到第一微电子器件的背面端子。 围绕第一微电子器件，EGP和EGP互连结构形成模制封装体。 模制包装体具有暴露EGP的前侧。 一个或多个再分配层形成在模制封装体的前侧，并且包含至少一个互连线，其通过EGP和背面EGP互连结构电耦合到背侧触点。

公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09281284B2

公开(公告)日：2016-03-08

申请号：US14310992

申请日：2014-06-20

申请人： Weng F. Yap ,  Zhiwei Gong

发明人： Weng F. Yap ,  Zhiwei Gong

IPC分类号： H01L23/58 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/52 ,  H01L23/552

CPC分类号： H01L23/66 ,  H01L21/52 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6622 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3025

摘要： System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

摘要翻译： 提供了系统级封装（SiP）和生产SiP的方法。 在一个实施例中，上述SiP制造方法包括在芯组件中形成通孔的步骤或工艺，所述芯组件包含暴露在通孔的侧壁表面处的电导通路径特征。 引线部件邻近芯部封装定位，使得引导部件的细长引线延伸到通孔中。 然后将诸如焊料的导电材料施加到通孔中以将引导部件的细长引线电耦合到芯部封装的导电路由特征。

公开(公告)号：US08980696B2

公开(公告)日：2015-03-17

申请号：US13292103

申请日：2011-11-09

申请人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

发明人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  A01J21/00 ,  A01J25/12 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

摘要翻译： 封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。 嵌入式单元是具有至少一个空腔的单个独立单元。 嵌入式单元被放置在过程安装表面的封装区域内和之内。 嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。 嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的管芯漂移，移动或歪斜。

公开(公告)号：US08916421B2

公开(公告)日：2014-12-23

申请号：US13222148

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L21/70 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 一个或多个信号管道耦合到引线框架，引线框架随后嵌入在封装的半导体器件封装中。 信号管道的自由端被暴露，而另一端保持联接到引线框架。 然后，信号导管用作通过封装通孔，在封装的底部和顶部与引线之间的互连或接触之间提供信号承载通路。

公开(公告)号：US20110217814A1

公开(公告)日：2011-09-08

申请号：US13125502

申请日：2008-10-23

申请人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

发明人： Wei Gao ,  Craig S. Amrine ,  Zhiwei Gong ,  Scott M. Hayes ,  Lizabeth Ann Keser ,  George R. Leal ,  William H. Lytle

IPC分类号： H01L21/78

CPC分类号： H01L21/67092 ,  H01L21/568 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68322 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

摘要翻译： 提供了形成电子组件的方法。 提供具有嵌入其中的多个电子部件的器件基板。 使用粘合剂材料将装置基板附接到载体基板。 通过器件基板形成多个切口，以将器件基板分成多个部分。 多个部分中的每一个包括至少一个电子部件。 在远离载体基板的方向上对多个部分中的每一个施加力以从载体基板移除多个部分。

公开(公告)号：US20160086930A1

公开(公告)日：2016-03-24

申请号：US14494611

申请日：2014-09-24

申请人： Dominic Koey ,  Zhiwei Gong

发明人： Dominic Koey ,  Zhiwei Gong

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511

摘要： Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.

摘要翻译： 扇出晶圆级封装（FO-WLP）包括双面模制封装体，其中第一和第二层部件以背对背的关系嵌入。 在一个实施例中，FO-WLP制造方法包括以由第二临时衬底承载的第二微电子部件的背对背关系定位由第一临时衬底承载的第一微电子部件。 第一和第二部件被包覆成型，同时以背对背的关系定位，以产生双面模制包装体。 然后去除第一临时衬底以暴露第一部件暴露于封装主体的第一主表面，并且同样去除第二临时衬底以露出封装体的第二相对主表面，在该第二部分处，第二部件 被暴露。

公开(公告)号：US09034697B2

公开(公告)日：2015-05-19

申请号：US13182710

申请日：2011-07-14

申请人： Zhiwei Gong ,  Jianwen Xu ,  Wei Gao ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Jianwen Xu ,  Wei Gao ,  Scott M. Hayes

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/568 ,  H01L21/4821 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

摘要翻译： 公开了一种用于制造半导体封装的方法，其包括提供引线元件的供应，将多个引线元件安装在引线框架上，直到将预定数量的引线元件放置在引线框架上，以及连接引线上的其它元件 框架到铅元素。