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    MEMORY DEVICE
    3.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20230292531A1

    公开(公告)日：2023-09-14

    申请号：US17690650

    申请日：2022-03-09

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Han LIN ,  Chia-En HUANG

    IPC分类号： H01L27/24 ,  H01L27/11514 ,  H01L27/22

    CPC分类号： H01L27/2454 ,  H01L27/11514 ,  H01L27/228

    摘要： A memory device includes two word-line electrodes, two source-line electrodes, and two data storage features for use by four memory cells, which are referred to as first, second, third and fourth memory cells. One word-line electrode is common to the first and second memory cells, and the other word-line electrode is common to the third and fourth memory cells. One source-line electrode is common to the first and second memory cells, and the other source-line electrode is common to the third and fourth memory cells. One data storage feature is common to the first and third memory cells, and the other data storage feature is common to the second and fourth memory cells.

    TECHNIQUES TO PERFORM A SENSE OPERATION
    4.
    发明公开
    TECHNIQUES TO PERFORM A SENSE OPERATION 审中-公开

    公开(公告)号：US20230206978A1

    公开(公告)日：2023-06-29

    申请号：US17646259

    申请日：2021-12-28

    申请人： Micron Technology, Inc.

    发明人： Umberto Di Vincenzo ,  Michele Maria Venturini

    IPC分类号： G11C11/22 ,  G11C7/12 ,  H01L27/11514

    CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C7/12 ,  H01L27/11514

    摘要： Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

    PLATE NODE CONFIGURATIONS AND OPERATIONS FOR A MEMORY ARRAY
    5.
    发明申请
    PLATE NODE CONFIGURATIONS AND OPERATIONS FOR A MEMORY ARRAY 审中-公开

    公开(公告)号：US20180331114A1

    公开(公告)日：2018-11-15

    申请号：US15969302

    申请日：2018-05-02

    申请人： Micron Technology, Inc.

    发明人： Daniele Vimercati

    IPC分类号： H01L27/11514 ,  G11C11/22

    CPC分类号： H01L27/11514 ,  G11C11/221 ,  G11C11/2259

    摘要： Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.