公开(公告)号：US20150021780A1

公开(公告)日：2015-01-22

申请号：US13946949

申请日：2013-07-19

Applicant: Yuping Gong ,  Yan Xun Xue ,  Ming-Chen Lu ,  Ping Huang ,  Jun Lu ,  Hamza Yilmaz

Inventor： Yuping Gong ,  Yan Xun Xue ,  Ming-Chen Lu ,  Ping Huang ,  Jun Lu ,  Hamza Yilmaz

IPC: H01L23/13 ,  H01L23/00

CPC classification number: H05K3/306 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/89 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/24101 ,  H01L2224/24147 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2224/92224 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/15153 ,  H05K3/32 ,  H05K3/4697 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/8384 ,  H01L2224/8485 ,  H01L2224/8385

Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.

Abstract translation: 薄功率器件包括衬底，衬底在衬底的前表面处具有第一组第一接触焊盘，电连接到衬底的背面处的第二组第二接触焊盘，从前表面开口并穿过 所述基板在所述基板的背面暴露第三接触焊盘，在所述第三接触焊盘的所述半导体芯片的后表面处嵌入所述通孔中的背面金属层的半导体芯片，以及多个导电结构， 将所述半导体芯片的前表面处的电极与所述第一组第一接触焊盘中的对应的第一接触焊盘连接。

公开(公告)号：US08933550B2

公开(公告)日：2015-01-13

申请号：US13442757

申请日：2012-04-09

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L23/22 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

Abstract translation: 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US08853003B2

公开(公告)日：2014-10-07

申请号：US13602144

申请日：2012-09-01

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  H01L23/492 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract translation: 一种形成具有厚底金属的晶片级芯片级（WLCS）封装器件的方法，包括将包括多个厚底金属的引线框架附接到半导体晶片的背金属层上的步骤，该半导体晶片包括多个半导体芯片， 形成在每个芯片的前表面上的多个接合焊盘，每个厚的底部金属与每个芯片的中心部分对准; 沿着划线形成多个后侧切割槽并填充有封装材料，从而切割包装材料从而形成多个单个WLCS封装装置。

公开(公告)号：US20140242756A1

公开(公告)日：2014-08-28

申请号：US13775212

申请日：2013-02-24

Applicant: Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

Inventor： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract translation: 一种用于在倒装芯片工艺中制备半导体器件的方法包括形成围绕每个半导体芯片的深槽; 沉积第一塑料封装材料以形成覆盖半导体晶片的前表面并填充深槽的第一塑料封装层; 在研磨后在半导体晶片的背面沉积金属层; 研磨金属层的最外部分，从而形成位于未被金属层覆盖的半导体晶片的边缘周围的背面的环形区域; 沿着由填充有第一塑料包装材料的每个深槽的两端形成的直线切割填充在深槽中的第一塑料封装层，半导体晶片，金属层和第一塑料封装材料; 并且拾取半导体器件并安装在衬底上，而不会翻转半导体器件。

公开(公告)号：US20140191334A1

公开(公告)日：2014-07-10

申请号：US13734201

申请日：2013-01-04

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC: H01L23/495 ,  H01L27/088

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L27/088 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract translation: 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US08722466B2

公开(公告)日：2014-05-13

申请号：US12722528

申请日：2010-03-12

Applicant: Jun Lu ,  Kai Liu ,  Yan Xun Xue

Inventor： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract translation: 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US20140091446A1

公开(公告)日：2014-04-03

申请号：US13631471

申请日：2012-09-28

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/498 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49861 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49172 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US08642397B1

公开(公告)日：2014-02-04

申请号：US13607775

申请日：2012-09-09

Applicant: Yuping Gong ,  Yan Xun Xue ,  Ping Huang

Inventor： Yuping Gong ,  Yan Xun Xue ,  Ping Huang

IPC: H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A wafer-level semiconductor package method comprising the step of providing a first wafer comprising a plurality of first dies each having a first, a second and a third electrodes formed on its front surface; attaching a second die having a fourth and a fifth electrodes formed on its front surface and a sixth electrode formed at its back surface onto each of the first die of the first wafer with the sixth electrode at the back surface of the second die attached and electrically connected to the second electrode at the front surface of the first die; and cutting the first wafer to singulate individual semiconductor packages.

Abstract translation: 一种晶片级半导体封装方法，包括提供包括多个第一裸片的第一晶片的步骤，所述第一晶片具有形成在其前表面上的第一，第二和第三电极; 将具有在其前表面上形成的第四和第五电极的第二管芯和在其后表面上形成的第六电极连接到第一晶片的每个第一管芯上，第二电极的后表面上的第六电极被附接并电连接 在第一模具的前表面处连接到第二电极; 并切割第一晶片以单独的半导体封装。

公开(公告)号：US08581376B2

公开(公告)日：2013-11-12

申请号：US12819111

申请日：2010-06-18

Applicant: Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

Inventor： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC: H01L21/44 ,  H01L21/31

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract translation: 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20130221507A1

公开(公告)日：2013-08-29

申请号：US13408185

申请日：2012-02-29

Applicant: Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

Inventor： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Abstract translation: 半导体封装设置有没有贵金属的铝合金引线框架，镀在铝基底引线框架上。 提供具有适当的合金组成和制造铝合金引线框架的比例的铝合金材料。 铝合金引线框架依次电镀有第一金属电镀层，第二电镀层和第三电镀层。 然后，利用第一，第二和第三金属电镀层电镀的引线框架用于包括芯片连接，引线接合和塑性模制的功率半导体封装的制造过程中。 在模制过程之后，未被模塑料覆盖的引线框架的区域用暴露于空气中不容易氧化的第四金属电镀层电镀。