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91.发明申请公开(公告)号：US20180138277A1
公开(公告)日：2018-05-17
申请号：US15852956
申请日：2017-12-22
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/417 , H01L29/66 , H01L21/28 , H01L29/78 , H01L21/02
CPC分类号： H01L29/41741 , H01L21/02266 , H01L21/28114 , H01L21/28123 , H01L21/3065 , H01L21/308 , H01L29/42392 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
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公开(公告)号：US09953977B1
公开(公告)日：2018-04-24
申请号：US15486432
申请日：2017-04-13
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/66 , H01L21/02 , H01L21/311 , H01L29/51
CPC分类号： H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Fabricating a semiconductor structure, including: forming a fin structure on a substrate by: forming a first fin layer on the substrate; forming a first insulator layer on the first fin layer; forming a second fin layer on the first insulator layer; forming a second insulator layer on the second fin layer; forming a third fin layer on the second insulator layer; and forming a gate structure on a plurality of opposing sides and a top surface of the fin structure.
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公开(公告)号：US09893171B2
公开(公告)日：2018-02-13
申请号：US15173006
申请日：2016-06-03
IPC分类号： H01L29/66 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/40 , H01L21/311 , H01L21/3213 , H01L21/02
CPC分类号： H01L29/66795 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/26513 , H01L21/3065 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/401 , H01L29/41791 , H01L29/42356 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
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公开(公告)号：US09761717B2
公开(公告)日：2017-09-12
申请号：US15223937
申请日：2016-07-29
发明人： Kangguo Cheng , Juntao Li , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L29/10 , H01L21/762 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/08 , H01L27/092
CPC分类号： H01L21/823412 , H01L21/265 , H01L21/26506 , H01L21/30604 , H01L21/3085 , H01L21/324 , H01L21/76205 , H01L21/76224 , H01L21/76237 , H01L21/823431 , H01L21/823481 , H01L21/84 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1054 , H01L29/6656 , H01L29/66795 , H01L29/66818 , H01L29/7847 , H01L29/7848 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
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公开(公告)号：US20170221991A1
公开(公告)日：2017-08-03
申请号：US15487675
申请日：2017-04-14
IPC分类号： H01L29/06 , H01L29/08 , H01L29/167 , H01L29/417 , H01L21/306 , H01L29/78 , H01L29/66 , H01L21/265 , H01L21/3105 , H01L29/423 , H01L29/161
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/02321 , H01L21/02332 , H01L21/265 , H01L21/26506 , H01L21/30604 , H01L21/3085 , H01L21/31051 , H01L21/31111 , H01L21/31155 , H01L21/76243 , H01L21/845 , H01L29/0649 , H01L29/0676 , H01L29/0847 , H01L29/161 , H01L29/167 , H01L29/41783 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device includes a semiconductor-on-insulator water having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
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公开(公告)号：US09716160B2
公开(公告)日：2017-07-25
申请号：US14449194
申请日：2014-08-01
IPC分类号： H01L21/336 , H01L29/45 , H01L29/66 , H01L21/285 , H01L29/417 , H01L21/768 , H01L21/311 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31111 , H01L21/31116 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L21/823418 , H01L21/823814 , H01L29/41783 , H01L29/66545 , H01L29/66628
摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.
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公开(公告)号：US20170047250A1
公开(公告)日：2017-02-16
申请号：US15338603
申请日：2016-10-31
IPC分类号： H01L21/768 , H01L23/535 , H01L21/8238 , H01L29/08 , H01L29/66 , H01L23/532 , H01L29/78
CPC分类号： H01L29/7845 , H01L21/76805 , H01L21/76889 , H01L21/76897 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/53266 , H01L23/535 , H01L29/0649 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.
摘要翻译： 描述了鳍状场效应晶体管（finFET）器件和制造finFET的方法。 该方法包括在侧壁间隔物的内壁之间的衬底上形成置换栅极叠层，在衬底上外延生长邻近侧壁间隔物的外壁的凸起源极漏极（RSD），以及在RSD上方并沿着外部形成硅化物 侧墙的墙壁。 该方法还包括在替代栅极堆叠和RSD的部分上方沉积和抛光接触金属，接触金属沿邻近替换栅极堆叠部分的侧壁间隔物的外壁接触硅化物。
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公开(公告)号：US20170040437A1
公开(公告)日：2017-02-09
申请号：US15298828
申请日：2016-10-20
发明人： Hong He , Chiahsun Tseng , Tenko Yamashita , Chun-Chen Yeh , Yunpeng Yin
CPC分类号： H01L29/66545 , H01L29/0649 , H01L29/0847 , H01L29/6653 , H01L29/66795 , H01L29/785
摘要： A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.
摘要翻译： 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。
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公开(公告)号：US09543407B2
公开(公告)日：2017-01-10
申请号：US14191751
申请日：2014-02-27
发明人： Hong He , Chiahsun Tseng , Tenko Yamashita , Chun-Chen Yeh , Yunpeng Yin
CPC分类号： H01L29/66545 , H01L29/0649 , H01L29/0847 , H01L29/6653 , H01L29/66795 , H01L29/785
摘要： A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.
摘要翻译： 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。
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公开(公告)号：US20160380054A1
公开(公告)日：2016-12-29
申请号：US15229690
申请日：2016-08-05
IPC分类号： H01L29/06 , H01L21/306 , H01L29/78 , H01L29/66 , H01L21/265 , H01L21/762 , H01L21/308
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/02321 , H01L21/02332 , H01L21/265 , H01L21/26506 , H01L21/30604 , H01L21/3085 , H01L21/31051 , H01L21/31111 , H01L21/31155 , H01L21/76243 , H01L21/845 , H01L29/0649 , H01L29/0676 , H01L29/0847 , H01L29/161 , H01L29/167 , H01L29/41783 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
摘要翻译： 半导体器件包括具有掩埋氧化物层的绝缘体上半导体晶片。 掩埋氧化物层在其中包括相对的蚀刻阻挡区域和蚀刻阻挡区域之间的栅极区域。 半导体器件还包括至少一个纳米线，其具有介于相对的源极/漏极部分之间的沟道部分。 通道部分悬挂在栅极区域中。 在栅极区域中形成栅电极，并且完全包围悬浮的纳米线的所有表面。 掩埋氧化物层包括第一电绝缘材料，并且蚀刻阻挡区域包括不同于第一电绝缘材料的第二电绝缘材料。
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