公开(公告)号：US07355282B2

公开(公告)日：2008-04-08

申请号：US10970871

申请日：2004-10-22

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Chiu-Ming Chou

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Chiu-Ming Chou

IPC分类号： H01L29/72

CPC分类号： H01L23/5223 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

公开(公告)号：US20080042297A1

公开(公告)日：2008-02-21

申请号：US11877658

申请日：2007-10-23

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/01074 ,  H01L2924/04953

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 在电介质层上沉积钝化层，并在钝化层的表面上形成厚的第二电介质层。 在厚的第二层电介质中产生厚而宽的后钝化互连线。 也可以消除第一层电介质，在已​​经沉积在衬底表面上的钝化层的表面上产生宽的厚钝化互连网络。

公开(公告)号：US20070246834A1

公开(公告)日：2007-10-25

申请号：US11818028

申请日：2007-06-13

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/62 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 在电介质层上沉积钝化层，并在钝化层的表面上形成厚的第二电介质层。 在厚的第二层电介质中产生厚而宽的后钝化互连线。 也可以消除第一层电介质，在已​​经沉积在衬底的表面上的钝化层的表面上产生宽厚的钝化互连网络。

公开(公告)号：US20070096313A1

公开(公告)日：2007-05-03

申请号：US11262184

申请日：2005-10-28

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/73 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05155 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/4943 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns

摘要翻译： 本发明提供一种包括在所述钝化层上的互连结构的半导体芯片。 互连结构包括连接到由钝化层中的开口暴露的第二接触焊盘的第一接触焊盘。 金属凸块位于第一接触焊盘上并且在多个半导体器件上，其中金属凸块具有超过50重量％的金并且具有在8和50微米之间的高度

公开(公告)号：US20060049524A1

公开(公告)日：2006-03-09

申请号：US10937543

申请日：2004-09-09

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/52

CPC分类号： H01L23/5329 ,  H01L23/3171 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014 ,  H01L2924/00012

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

公开(公告)号：US20060022343A1

公开(公告)日：2006-02-02

申请号：US11087955

申请日：2005-03-23

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L21/76829 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

公开(公告)号：US20050277283A1

公开(公告)日：2005-12-15

申请号：US11202730

申请日：2005-08-12

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC分类号： H01L21/4763 ,  H01L21/60 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L23/3192 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01039 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.

摘要翻译： 一种用于制造金属化结构的方法包括沉积第一金属层; 在所述第一金属层上沉积第一图案界定层，所述第一图案限定层中的第一开口暴露所述第一金属层; 在由所述第一开口暴露的所述第一金属层上沉积第二金属层; 在所述第二金属层上沉积第二图案限定层，所述第二图案限定层中的第二开口露出所述第二金属层; 在由所述第二开口暴露的所述第二金属层上沉积第三金属层; 去除所述第二图案限定层; 去除所述第一图案限定层; 以及不在所述第二金属层下方去除所述第一金属层。

公开(公告)号：US09030029B2

公开(公告)日：2015-05-12

申请号：US10055568

申请日：2002-01-22

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L29/00 ,  H01L29/40 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L24/97 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

摘要翻译： 集成芯片封装结构及其制造方法是通过在硅基板上附着模具并在芯片和硅基板的顶部上形成薄膜电路层。 其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。 此外，多个有源器件和内部电路位于管芯的有效表面上。 有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。 此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

公开(公告)号：US08492870B2

公开(公告)日：2013-07-23

申请号：US13159190

申请日：2011-06-13

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L29/00 ,  H01L21/00 ,  H05K7/00

CPC分类号： H01L24/19 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.

摘要翻译： 一种包括玻璃基板的芯片封装件，其中所述玻璃基板中的第一开口垂直穿过所述玻璃基板，半导体芯片，包括所述第一开口中的第一部分和所述玻璃基板上的第二部分的布线结构，其中所述第一 部分连接到半导体芯片，其中布线结构包括无源器件，其中布线结构包括铜，以及在玻璃衬底上和布线结构上的电介质层，其中电介质层中的第二开口在触点上方 接点位于第二开口的底部。

公开(公告)号：US08384508B2

公开(公告)日：2013-02-26

申请号：US13077009

申请日：2011-03-31

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01F5/00 ,  H01F27/28

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/5227 ,  H01L28/10 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.

摘要翻译： 提供了一种新的制造半导体电感器的方法和结构。 在本发明的第一实施例中，半导体衬底在无源表面区域中设有划线，并且在被动区域周围设有有源电路。 在基板的被动表面上至少形成一个接合垫，该接合垫靠近划线的每侧。 沉积一层绝缘层，在该绝缘层上沉积一层电介质，至少一个接合焊盘设置在刻划线两边的电介质层的表面上。 在电介质层的表面上的划线的每侧形成至少一个电感器。 一层钝化层沉积在电介质层上。 通过将钝化层的表面与玻璃面板接合来将衬底附接到玻璃面板。 衬底从衬底的背面锯切，与划刻线对准。 通过蚀刻去除在划线下面的衬底的被动表面中残留的位置的硅，沿着划线分离玻璃面板。 在本发明的第二个实施例中，电感器被形成在沉积在钝化层上的聚合物厚层的表面上。