公开(公告)号：US20240153896A1

公开(公告)日：2024-05-09

申请号：US18411314

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Hui-Min Huang ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/05 ,  H01L21/481 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/18162

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

公开(公告)号：US20240153842A1

公开(公告)日：2024-05-09

申请号：US18404504

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2924/15311

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US11935804B2

公开(公告)日：2024-03-19

申请号：US18297927

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/16 ,  H01L23/5226 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11901258B2

公开(公告)日：2024-02-13

申请号：US17227790

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L23/50 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US20230378253A1

公开(公告)日：2023-11-23

申请号：US18358399

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L29/7848 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11545465B2

公开(公告)日：2023-01-03

申请号：US17113676

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US11532498B2

公开(公告)日：2022-12-20

申请号：US16934394

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Hui-Min Huang ,  Ai-Tee Ang ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L25/065

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

公开(公告)号：US11456226B2

公开(公告)日：2022-09-27

申请号：US16858737

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US11233039B2

公开(公告)日：2022-01-25

申请号：US16866561

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Yang ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Yu-Hao Chen

IPC: H01L25/16 ,  H01L23/498

Abstract: Semiconductor packages are provided. The semiconductor package includes a first redistribution layer structure, a photonic integrated circuit, an electronic integrated circuit, a waveguide and a memory. The photonic integrated circuit is disposed over and electrically connected to the first redistribution layer structure, and includes an optical transceiver and an optical coupler. The electronic integrated circuit is disposed over and electrically connected to the first redistribution layer structure. The waveguide is optically coupled to the optical coupler. The memory is electrically connected to the electronic integrated circuit.

公开(公告)号：US20210233854A1

公开(公告)日：2021-07-29

申请号：US17215079

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.