公开(公告)号：US12288729B2

公开(公告)日：2025-04-29

申请号：US18435362

申请日：2024-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US12266619B2

公开(公告)日：2025-04-01

申请号：US18358991

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/10 ,  H01P3/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q9/04 ,  H01Q21/06

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US12210200B2

公开(公告)日：2025-01-28

申请号：US18586919

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ming Weng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Hung-Yi Kuo ,  Tsung-Yuan Yu ,  Hua-Kuei Lin ,  Che-Hsiang Hsu

IPC: G02B6/43 ,  G02B6/42

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

公开(公告)号：US20240405005A1

公开(公告)日：2024-12-05

申请号：US18783688

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/40

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US20240395769A1

公开(公告)日：2024-11-28

申请号：US18783555

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Shu-Rong Chun ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

公开(公告)号：US20240395566A1

公开(公告)日：2024-11-28

申请号：US18790326

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US20240386744A1

公开(公告)日：2024-11-21

申请号：US18789792

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chih-Hua Chen ,  Yu-Jen Cheng ,  Chih-Wei Lin ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G06V40/13 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

公开(公告)号：US20240371818A1

公开(公告)日：2024-11-07

申请号：US18310293

申请日：2023-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Jui Hsuan Tsai ,  Chiao-Chun Chang ,  Chu-Chuan Huang ,  Jih-Churng Twu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/538

Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.

公开(公告)号：US12074127B2

公开(公告)日：2024-08-27

申请号：US18059148

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/482 ,  H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L23/53228 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2924/013

Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

公开(公告)号：US12009345B2

公开(公告)日：2024-06-11

申请号：US18149509

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.