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102 条记录 (耗时 0.031 秒)

    Oxide protection for a booster circuit
    91.
    发明授权
    Oxide protection for a booster circuit 有权
    升压电路的氧化物保护

    公开(公告)号：US06487060B1

    公开(公告)日：2002-11-26

    申请号：US09916382

    申请日：2001-07-27

    申请人： Takao Akaogi

    发明人： Takao Akaogi

    IPC分类号： H02H322

    CPC分类号： G11C5/145

    摘要： A protection system that protects a booster circuit used to boost operating signals in a memory device. The system includes a protection circuit for protecting an output transistor of the booster circuit. The protection circuit includes a transfer gate coupled to the output transistor and coupled to receive a first boost signal and a second boost signal. The transfer gate opens and closes in response to the second boost signal. When the transfer gate is closed, the first boost signal is uncoupled from the output transistor, and when the transfer gate is opened, the first boost signal is coupled to the output transistor. The circuit also includes a protection transistor coupled to the second boost signal, a supply voltage and the output transistor, where the protection transistor couples the supply voltage to the output transistor when the transfer gate is closed.

    摘要翻译： 保护系统，其保护用于升高存储器件中的操作信号的升压电路。 该系统包括用于保护升压电路的输出晶体管的保护电路。 保护电路包括耦合到输出晶体管并被耦合以接收第一升压信号和第二升压信号的传输栅极。 转移门响应于第二升压信号而打开和关闭。 当传输门关闭时，第一升压信号与输出晶体管分离，当传输门断开时，第一升压信号耦合到输出晶体管。 电路还包括耦合到第二升压信号的保护晶体管，电源电压和输出晶体管，其中当传输门关闭时，保护晶体管将电源电压耦合到输出晶体管。

    Power saving scheme for burst mode implementation during reading of data from a memory device
    92.
    发明授权
    Power saving scheme for burst mode implementation during reading of data from a memory device 有权
    在从存储器件读取数据期间突发模式实现的省电方案

    公开(公告)号：US06463003B2

    公开(公告)日：2002-10-08

    申请号：US09729388

    申请日：2000-12-04

    申请人： Ali K. Al-Shamma ,  Takao Akaogi

    发明人： Ali K. Al-Shamma ,  Takao Akaogi

    IPC分类号： G11C800

    CPC分类号： G11C7/1069 ,  G11C7/1021 ,  G11C7/1051

    摘要： Reading data from a core memory consumes more power when the data sets being driven change state, especially when bursting out the data at high speed. Power saving for a burst mode implementation improves the power consumed by inverting the data sets whenever a majority of the data changes states from set to set and including a separate output indicating whether the data being driven is inverted. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data. Thus, power is saved as the state of the majority of the data being driven from one data set to the next remains unchanged.

    摘要翻译： 当驱动的数据组改变状态时，从核心存储器读取数据会消耗更多的电力，特别是当高速突发数据时。 突发模式实现的省电改善了每当数据的大多数从设置到设置状态改变时包括反转数据组所消耗的功率，并且包括指示被驱动的数据是否被反转的单独的输出。 现有数据从核心存储器中选择并计入省电布置。 将当前数据与先前选择的数据进行比较，以确定当前选择的大部分数据是否已从先前选择的数据改变。 此外，当前选择的数据也被延迟，然后经过上述多数确定的逻辑XOR功能。 最后，经过逻辑异或功能和多数确定的数据被分别驱动到请求本数据的外部元件。 因此，由于从一个数据集驱动到下一个数据的大部分数据的状态保持不变，所以节省了功率。

    Power-saving modes for memories
    93.
    发明授权
    Power-saving modes for memories 有权

    公开(公告)号：US06400633B1

    公开(公告)日：2002-06-04

    申请号：US09675372

    申请日：2000-09-29

    申请人： Ali Al-Shamma ,  Takao Akaogi ,  Lee Cleveland

    发明人： Ali Al-Shamma ,  Takao Akaogi ,  Lee Cleveland

    IPC分类号： G11C700

    CPC分类号： G11C7/00 ,  G11C7/1006 ,  G11C7/1072 ,  G11C2207/2263

    摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

    Address transition detect timing architecture for a simultaneous operation flash memory device
    94.
    发明授权
    Address transition detect timing architecture for a simultaneous operation flash memory device 有权
    用于同时运行的闪存设备的地址转换检测定时架构

    公开(公告)号：US06208556B1

    公开(公告)日：2001-03-27

    申请号：US09547556

    申请日：2000-04-12

    申请人： Takao Akaogi ,  Kazuhiro Kurihara ,  Tien-Min Chen

    发明人： Takao Akaogi ,  Kazuhiro Kurihara ,  Tien-Min Chen

    IPC分类号： G11C1604

    CPC分类号： G11C16/32 ,  G11C8/12 ,  G11C8/18

    摘要： An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.

    摘要翻译： 公开了一种用于双银行闪存设备的地址转换信号发生器。 发生器包括信号转换检测器，其监视器件的控制信号用于其逻辑值中的转换。 在检测到信号转换时，转换检测器通过等距信号路径向bank地址转换检测信号发生器电路发送信号。 这导致从每个存储体地址转换检测信号发生器电路同时生成地址转换检测信号。

    Nonvolatile semiconductor memory with pre-read means
    98.
    发明授权
    Nonvolatile semiconductor memory with pre-read means 失效
    具有预读功能的非易失性半导体存储器

    公开(公告)号：US5572463A

    公开(公告)日：1996-11-05

    申请号：US416281

    申请日：1995-04-04

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group of data pieces according the another address to be provided by the first address generation means while the preceding data pieces are being read according to the preceding address provided by the first address generation means and being selectively provided to the output buffer according to the addresses provided by the second address generation means.

    摘要翻译： 具有地址缓冲器装置，存储单元装置，字线选择装置，位线选择装置，输出缓冲器，连接到地址缓冲器装置的第一地址产生装置的半导体存储器，用于提供和寻址用于指定一组数据片段，以及 第二地址产生装置，分别提供用于指定数据片段的地址，所述半导体存储器包括第一读取装置，用于根据由字线选择装置和位线选择装置中的一个选择和读取一组数据片段， 第一地址产生装置，用于根据由第一地址产生装置提供的地址选择和读取的数据片段的第二地址产生装置，通过位线选择装置和字线选择装置之一，根据由 第二地址产生装置并将其提供给输出缓冲器; 以及预读取装置，用于根据由第一地址产生装置提供的另一地址读取另一组数据片段，同时根据由第一地址产生装置提供的先前地址读取先前的数据，并且选择性地提供给 所述输出缓冲器根据由所述第二地址产生装置提供的地址。

    Non-volatile semiconductor memory device having floating gate
    99.
    发明授权
    Non-volatile semiconductor memory device having floating gate 失效
    具有浮动栅极的非易失性半导体存储器件

    公开(公告)号：US5521866A

    公开(公告)日：1996-05-28

    申请号：US244634

    申请日：1994-09-02

    申请人： Takao Akaogi

    发明人： Takao Akaogi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    CPC分类号： G11C16/16 ,  G11C16/0416 ,  H01L27/115

    摘要： A non-volatile semiconductor memory device includes a semiconductor substrate with a first conductivity type, a first well of a second conductivity type formed on the semiconductor substrate, a second well of the first conductivity type formed on the first well, a plurality of memory cells provided in the second well and each including a tunneling insulation film having a thickness allowing a tunneling of carriers, a floating gate electrode provided on the tunneling insulation film, an interlayer insulation film provided on the floating gate electrode, a control electrode provided on the interlayer insulation film, and a pair of diffusion regions of the first conductivity type formed on the second well at both sides of a channel region. An erasing circuit is provided for dissipating electric charges held in the floating gate electrode into the channel region through the tunneling insulation film in the form of a tunneling current, wherein the erasing circuit applies, in response to a start signal indicative of commencement of erasing, a first erase signal to the first well and a second erase signal having a polarity identical to the first erase signal to the second well, such that the first erase signal is applied in advance to the second erase signal.

    摘要翻译： PCT No.PCT / JP93 / 01438 Sec。 371日期：1994年9月2日 102（e）1994年9月2日PCT PCT 1993年10月6日PCT公布。 出版物WO94 / 08340 日本1994年4月14日。非易失性半导体存储器件包括具有第一导电类型的半导体衬底，形成在半导体衬底上的第二导电类型的第一阱，第一导电类型的第一阱形成在第一导电类型 以及设置在第二阱中的多个存储单元，每个存储单元包括具有允许载流子隧穿的厚度的隧道绝缘膜，设置在隧道绝缘膜上的浮栅电极，设置在浮栅电极上的层间绝缘膜， 设置在层间绝缘膜上的控制电极，以及形成在沟道区域两侧的第二阱上的一对第一导电类型的扩散区域。 提供擦除电路，用于以隧道电流的形式通过隧道绝缘膜将保持在浮栅电极中的电荷消散到沟道区中，其中擦除电路响应于指示擦除开始的起始信号， 到第一阱的第一擦除信号和具有与第一擦除信号至第二阱极性相同的第二擦除信号，使得第一擦除信号预先施加到第二擦除信号。