公开(公告)号：US20100127367A1

公开(公告)日：2010-05-27

申请号：US12356547

申请日：2009-01-21

申请人： Shih-Wen Chou

发明人： Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L21/00 ,  H01L21/98 ,  H01L23/48

CPC分类号： H01L23/49558 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided.

摘要翻译： 包括电路基板，芯片，B阶粘合剂层，引线框架，多个第一接合线，多个第二接合线和多个第三接合线的芯片封装。 芯片设置在电路基板上。 B层粘合剂层设置在电路基板上。 引线框设置在电路基板上并且包括多个引线。 引线的一部分嵌入在B级粘合剂层中，并且每个引线的端部被B阶粘合剂层暴露。 第一接合线电连接在芯片和电路基板之间。 第二接合线电连接在芯片和引线之间。 第三接合线电连接在引线和电路基板之间。 此外，还提供了芯片封装的制造方法。

公开(公告)号：US07662672B2

公开(公告)日：2010-02-16

申请号：US12153451

申请日：2008-05-19

申请人： Hung-Tsun Lin

发明人： Hung-Tsun Lin

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/4828 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49534 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S438/94 ,  Y10S438/959 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

摘要翻译： 公开了一种基于引线框架的BGA封装的制造工艺。 为封装提供了具有上层和下层的无引线框架。 上层包括多个球垫，下层包括与球垫对准并连接的多个牺牲垫。 在上层或下层中形成多个引线以互连球垫或牺牲垫。 形成密封剂以在芯片附接和电连接之后嵌入球垫。 在制造过程中，在封装之后执行半蚀刻工艺以去除牺牲焊盘，以使球垫与密封剂电隔离并暴露于焊球放置处，其中限定了焊盘的焊接区域，而不需要焊接掩模 以解决在回流期间引线上的焊球渗漏或不期望的斑点的问题。 此外，可以容易地检测和去除模具闪光。

公开(公告)号：US07642639B2

公开(公告)日：2010-01-05

申请号：US11583951

申请日：2006-10-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

IPC分类号： H01L23/04 ,  H01L23/48

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49572 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

摘要翻译： 一种用于增强嵌入式凸块的结合性的IC封装，主要包括具有多个凸块容纳孔，凸起芯片，密封剂和多个外部端子的基板。 基板还分别在凸块容纳孔的一​​端具有多个内垫。 内部焊盘可以是啮合的，或者在其上设置焊接层以改善凸块连接。 芯片被附接到基板上，凸块对准并嵌入在相应的凸起容纳孔中。 密封剂至少形成在基底的下表面上以封装网眼或焊接层。 通过悬挂的网格或/和焊接层，可以在较低的温度下容易地接合凸块，以简化具有更短导电路径和更薄的封装形状的制造工艺，而无需扫线。

公开(公告)号：US20090321988A1

公开(公告)日：2009-12-31

申请号：US12555159

申请日：2009-09-08

申请人： Po-Kai Hou

发明人： Po-Kai Hou

IPC分类号： H01L21/56

CPC分类号： H01L21/565 ,  H01L21/566 ,  H01L23/3121 ,  H01L2224/48091 ,  H01L2924/00014

摘要： In a chip packaging process, an upper and a lower mold chases are provided. A thickness adjusting film is then provided below the upper mold chase and/or above the lower mold chase. Next, a carrier is delivered to a position between the upper and the lower mold chases. A chip and a conductive line are disposed on the carrier, and the thickness adjusting film is located between the upper mold chase and the carrier and/or between the lower mold chase and the carrier. The upper and the lower mold chases are attached to define a cavity, and the thickness adjusting film is located on the surface of the upper mold chase and/or the surface of the lower mold chase. Thereafter, a molding compound is provided into the cavity by using a molding compound supplying unit. The upper and the lower mold chases and the thickness adjusting film are removed.

摘要翻译： 在芯片封装过程中，提供上模和下模。 然后在上模具下方和/或下模具上方提供厚度调节膜。 接下来，将载体输送到上模和下模之间的位置。 芯片和导线设置在载体上，并且厚度调节膜位于上模追索和载体之间和/或下模移动和载体之间。 上模具和下模具附接以限定空腔，并且厚度调节膜位于上模追逐的表面和/或下模具的表面上。 此后，通过使用模塑料供给单元将模塑料提供到空腔中。 去除上下模具和厚度调节膜。

公开(公告)号：US07622806B2

公开(公告)日：2009-11-24

申请号：US11249465

申请日：2005-10-14

申请人： Shu-Ling Su ,  A-Tsung Cheng

发明人： Shu-Ling Su ,  A-Tsung Cheng

IPC分类号： H01L23/48

CPC分类号： H01L23/544 ,  B23K26/351 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  H01L2223/54406 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： A laser mark is inscribed on an IC component, which character stroke consists of a plurality of laser paths inscribed by a laser beam. The width of the character stroke is greater than the widths of the laser paths. In addition, at least two of the laser paths, moving in opposite directions or in a same direction of the laser beam, are integrally connected as a laser-inscribing stroke to reduce end-to-end breaks between the laser paths.

摘要翻译： 激光标记被刻在IC部件上，该字符行程由激光束内切的多个激光路径组成。 字符行程的宽度大于激光路径的宽度。 此外，沿着激光束的相反方向或相同方向移动的至少两个激光路径作为激光刻印行程被整体连接，以减少激光路径之间的端到端断裂。

公开(公告)号：US07609053B2

公开(公告)日：2009-10-27

申请号：US12061781

申请日：2008-04-03

申请人： Wen Cheng Hsu ,  Min Ming Lo ,  Chao Chien Wang ,  Yi Fang Cho

发明人： Wen Cheng Hsu ,  Min Ming Lo ,  Chao Chien Wang ,  Yi Fang Cho

IPC分类号： G01R31/28 ,  G06F17/00 ,  G08B13/14 ,  G06F7/00

CPC分类号： G01R31/01 ,  G01R31/2893

摘要： This invention provides a wafer testing system and testing method thereof. The wafer testing system comprises a wafer storage section, a prober, a tester, an RFID middleware unit, an EDA system and an MES system. The wafer storage section stores a multiplicity of carriers, each of which is provided with at least a RFID tag. The prober comprises a RFID reader to read a tag information. The tester sends a test signal to the prober for implementing the wafer test so as to generate a test result and calls an interface program to convert the test result into a file conformed with a specific data format. The RFID middleware unit receives the tag information and calls related applications to process the tag information so as to generate a wafer information. The EDA system receives the file of the specific data format converted from the interface program and calculates thereof to generate a wafer yield information after wafer test. The MES system integrates the wafer information from the RFID middleware unit with the yield information from the EDA system so as to allow monitoring the wafer manufacturing process and testing yield rate in a real-time manner.

摘要翻译： 本发明提供了一种晶片测试系统及其测试方法。 晶片测试系统包括晶片存储部分，探测器，测试器，RFID中间件单元，EDA系统和MES系统。 晶片存储部存储多个载体，每个载体至少设有RFID标签。 该探测器包括读取标签信息的RFID读取器。 测试仪将测试信号发送到探测器，以实现晶片测试，以产生测试结果，并调用接口程序将测试结果转换为符合特定数据格式的文件。 RFID中间件单元接收标签信息并调用相关应用程序来处理标签信息以产生晶片信息。 EDA系统接收从接口程序转换的特定数据格式的文件，并计算它们以在晶片测试之后生成晶片产量信息。 MES系统将RFID中间件单元的晶圆信息与EDA系统的产量信息相集成，以便实时监控晶圆制造过程和测试成品率。

公开(公告)号：US07605461B2

公开(公告)日：2009-10-20

申请号：US11755753

申请日：2007-05-31

申请人： Yu-Tang Pan ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L23/495 ,  H01L24/31 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

摘要翻译： 提供包括电路图案，框架，第一粘合剂层，多个引线，绝缘粘合剂层，芯片，多个第一接合线，多个第二接合线和模制化合物的芯片封装结构 。 框架和引线设置在电路图案周围。 第一粘合层紧固框架和电路图案。 绝缘粘合剂层设置在引线和框架之间。 芯片具有多个接合焊盘并设置在第一粘合剂层上。 第一接合线将接合焊盘分别电连接到电路图案。 第二接合线将引线单独地电连接到电路图案。 因此，接合焊盘通过第一接合线，电路图案和第二接合线与引线电连接。 模塑料覆盖上述组分。

公开(公告)号：US20090243056A1

公开(公告)日：2009-10-01

申请号：US12480105

申请日：2009-06-08

申请人： Wu-Chang Tu ,  Geng-Shin Shen

发明人： Wu-Chang Tu ,  Geng-Shin Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

摘要翻译： 具有不对称模制的芯片封装包括引线框架，芯片，粘合剂层，接合线和模塑料。 引线框架包括湍流板和具有内引线部分和外引线部分的框体。 湍流板向下弯曲以形成凹部。 湍流板的第一端连接到框体，第二端低于内引线部。 芯片通过粘合剂层固定在内引线部分的下方。 接合线连接在芯片和内引线部分之间。 模塑料封装芯片，接合线和湍流板。 凹形部分上方和下方的模塑料的厚度之比大于1.外引线部分之下和之上的模塑料的厚度不相等。

公开(公告)号：US07592694B2

公开(公告)日：2009-09-22

申请号：US11746064

申请日：2007-05-09

申请人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

IPC分类号： H01L23/495

CPC分类号： H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit layer has a plurality of conductive traces. The chip disposed above the metal layer is electrically connected to the conductive traces. The lead matrix having a plurality of leads is disposed outside the chip. At least part of the leads are electrically connected to the conductive traces. The encapsulant at least encapsulates the chip, the film-like circuit layer, at least part of the leads, and at least part of the metal layer.

摘要翻译： 提供了包括金属层，膜状电路层，芯片，引线基体和密封剂的芯片封装。 设置在金属层上的膜状电路层包括设置在金属层上的绝缘膜和设置在绝缘膜上的电路层。 电路层具有多个导电迹线。 设置在金属层上方的芯片电连接到导电迹线。 具有多个引线的引线矩阵设置在芯片外部。 引线的至少一部分电连接到导电迹线。 密封剂至少封装芯片，膜状电路层，引线的至少一部分以及金属层的至少一部分。

公开(公告)号：US07586200B2

公开(公告)日：2009-09-08

申请号：US11302737

申请日：2005-12-13

申请人： Jiunheng Wang

发明人： Jiunheng Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L33/46 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/12 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2224/05552

摘要： A light emitting diode including a substrate, a semiconductor layer, multiple electrodes, a passivation layer, multiple under bump metallurgy (UBM) layers and a reflective layer is provided. The semiconductor layer is disposed on the substrate. The electrodes and the passivation layer are disposed on the semiconductor layer. The passivation layer has multiple openings for exposing the electrodes. The UBM layers are disposed on the electrodes. The reflective layer is disposed on the passivation layer. The reflective layer is electrically isolated from the electrodes and the UBM layers. A method of fabricating the light emitting diode is also provided. The reflective layer and the UBM layers are fabricated simultaneously in one process. Therefore, the fabricating method is compatible with the existing process.

摘要翻译： 提供了包括衬底，半导体层，多个电极，钝化层，多个凸块下冶金（UBM）层和反射层的发光二极管。 半导体层设置在基板上。 电极和钝化层设置在半导体层上。 钝化层具有用于暴露电极的多个开口。 UBM层设置在电极上。 反射层设置在钝化层上。 反射层与电极和UBM层电隔离。 还提供了一种制造发光二极管的方法。 在一个过程中同时制造反射层和UBM层。 因此，制造方法与现有工艺兼容。