公开(公告)号：US09917157B2

公开(公告)日：2018-03-13

申请号：US15303231

申请日：2015-10-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  SOUTH CHINA UNIVERSITY OF TECHNOLOGY

Inventor： Guangcai Yuan ,  Liangchen Yan ,  Xiaoguang Xu ,  Lei Wang ,  Junbiao Peng ,  Linfeng Lan

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing method, and a display device. The method for manufacturing the TFT includes a step of forming a pattern of a semiconductor active layer on a transparent substrate through a patterning process, and the pattern of the semiconductor active layer includes a lanthanum boride pattern.

公开(公告)号：US20180069129A1

公开(公告)日：2018-03-08

申请号：US15704063

申请日：2017-09-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： YONG SU LEE ,  YOON HO KHANG ,  DONG JO KIM ,  HYUN JAE NA ,  SANG HO PARK ,  SE HWAN YU ,  CHONG SUP CHANG ,  DAE HO KIM ,  JAE NEUNG KIM ,  MYOUNG GEUN CHA ,  SANG GAB KIM ,  YU-GWANG JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20180059491A1

公开(公告)日：2018-03-01

申请号：US15026253

申请日：2016-02-25

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Xiangyang Xu

IPC: G02F1/1343 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/786 ,  H01L21/306 ,  H01L21/308 ,  H01L29/51 ,  H01L29/45 ,  H01L21/311 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134363 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/122 ,  G02F2201/123 ,  G02F2202/103 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78696

Abstract: The present invention provides a manufacture method of an IPS TFT-LCD array substrate and an IPS TFT-LCD array substrate. In the manufacture method of the IPS TFT-LCD array substrate, the common electrode line and the gate are manufactured with the same metal layer, and the pixel electrode and the drain are manufactured with the same metal layer, and the via is formed in the insulation protective layer and the gate isolation layer correspondingly above the common electrode line; in the TFT array substrate, the pixel electrode and the drain are manufactured with the same metal layer, and the common electrode line and the gate are manufactured with the same metal layer, and the common electrode is transparent conductive material and located on the insulation protective layer, and the common electrode contact with the common electrode line through the via in the insulation protective layer and the gate isolation layer.

公开(公告)号：US20180059456A1

公开(公告)日：2018-03-01

申请号：US15518911

申请日：2016-10-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Yunhai WAN ,  Chengshao YANG ,  Ling HAN ,  Botao SONG

IPC: G02F1/1368 ,  H01L21/28 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49

CPC classification number: G02F1/1368 ,  H01L21/0274 ,  H01L21/28 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/49 ,  H01L29/786 ,  H01L29/78636

Abstract: A manufacturing method of the invention, comprising: successively forming an insulation layer and a photoresist layer on a transparent substrate; performing an exposure and a development on the photoresist layer by a back exposure process, so as to form a trench in the photoresist layer, an open area of the trench proximal to the insulation layer is larger than that of the trench distal to the insulation layer; removing a portion of insulation material in a region of the insulation layer exposed through the trench by an etching process, so as to form a slot in the insulation layer; forming a metal layer on a side of the photoresist layer distal to the insulation layer, a portion of the metal layer is embedded in the slot; removing the photoresist layer and the metal layer thereon by a stripping process, and retaining the portion of the metal layer in the slot.

公开(公告)号：US20180052373A1

公开(公告)日：2018-02-22

申请号：US14915237

申请日：2016-01-28

Applicant: Wuhan China Star Optoelectronics Technology Ltd.

Inventor： Mian ZENG

IPC: G02F1/1362 ,  G02F1/1368 ,  G02F1/1343 ,  H01L27/12

CPC classification number: G02F1/136227 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2201/123 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/1288 ,  H01L27/1292

Abstract: This disclosure provides a COA substrate includes a substrate, and a gate, a gate dielectric layer, an active layer, a source, a drain, a first passivation layer, a color blocking layer, a second passivation layer, and a transparent conductive layer are formed on the substrate in order subsequently. A first hole is formed in the color blocking layer to expose the first passivation layer. The second passivation layer is disposed on the color blocking layer and in the first hole. A second hole is formed in the first hole to punch through the first passivation layer and the second passivation layer for exposing the drain and the source. A conductive fill-in material layer is formed in the first hole and the second hole. The aperture rate is increased and the bubble failure is improved and the pixel electrode disconnection due to the height gap is reduced in the present disclosure.

公开(公告)号：US20180046046A1

公开(公告)日：2018-02-15

申请号：US15511702

申请日：2016-03-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Bo FENG ,  Qing MIAO ,  Yu MA

IPC: G02F1/1362 ,  H01L21/768 ,  G02F1/1343 ,  H01L29/417 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/136227 ,  G02F1/13439 ,  G02F1/1368 ,  H01L21/28 ,  H01L21/76804 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/41733

Abstract: An array substrate includes a plurality of pixel regions, each of which includes: a pixel electrode and a drain electrode arranged on a same layer and independent from each other. The pixel electrode and the drain electrode are connected by a conductive part that is arranged on a different layer from the layer which the pixel electrode and the drain electrode are arranged on. The pixel electrode, the drain electrode and the conductive part are separated from each other by an insulation layer. A first via hole and a second via hole penetrating through the insulation layer are formed in the insulation layer at a position corresponding to the drain electrode and at a position corresponding to the pixel electrode, respectively. The drain electrode is connected to the conductive part through the first via hole, and the pixel electrode is connected to the conductive part through the second via hole.

公开(公告)号：US09893096B2

公开(公告)日：2018-02-13

申请号：US14760750

申请日：2015-06-17

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  WUHAN CHINA STAR OPTOELECTRONICE TECHNOLOGY CO., LTD

Inventor： Cong Wang ,  Peng Du

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L21/28 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78678

Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.

公开(公告)号：US20180033642A1

公开(公告)日：2018-02-01

申请号：US15325117

申请日：2015-12-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Xiaoyong LU ,  Dong LI ,  Xiaolong LI ,  Chunping LONG

IPC: H01L21/3205 ,  H01L29/45 ,  C23C14/00 ,  C23C14/14 ,  C23C14/34 ,  C23C14/06 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/32051 ,  C23C14/0073 ,  C23C14/0641 ,  C23C14/14 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/7685 ,  H01L21/76895 ,  H01L23/53223 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458

Abstract: The present disclosure provides a thin film transistor, a thin film transistor array substrate, and a display apparatus, and their fabrication methods. The thin film transistor is formed by forming a source and drain electrode structure. To form the source and drain electrode structure, at least one metal film is formed using a target of a metal element in a sputtering chamber. A gas is introduced in the sputtering chamber to in-situ react with the metal element to form an anti-reflection layer over the at least one metal film.

公开(公告)号：US09882055B2

公开(公告)日：2018-01-30

申请号：US15616931

申请日：2017-06-08

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Yue Wu

IPC: H01L29/786 ,  H01L21/84 ,  H01L21/02 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/02115 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02584 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/06 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a TFT substrate structure is provided, in which a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer. The modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone. Portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserve the excellent electrical conduction property of graphene to provide electrical connection between the source and drain electrodes and the semiconductor layer.

公开(公告)号：US20180026057A1

公开(公告)日：2018-01-25

申请号：US15647518

申请日：2017-07-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Lei ZHANG ,  Jiapeng LI ,  Jing ZHANG ,  Lei CHEN ,  Dongjiang SUN

IPC: H01L27/142 ,  H01L27/12

CPC classification number: H01L27/142 ,  H01L27/1288

Abstract: An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.