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    Perovskite-based thin film structures on miscut semiconductor substrates
    92.
    发明申请
    Perovskite-based thin film structures on miscut semiconductor substrates 审中-公开
    在半导体衬底上的基于钙钛矿的薄膜结构

    公开(公告)号：US20060288928A1

    公开(公告)日：2006-12-28

    申请号：US11149951

    申请日：2005-06-10

    申请人： Chang-Beom Eom ,  Darrell Schlom

    发明人： Chang-Beom Eom ,  Darrell Schlom

    IPC分类号： B32B9/00 ,  B32B19/00 ,  B32B13/04 ,  C30B23/00 ,  C30B28/14 ,  C30B25/00 ,  C30B28/12

    CPC分类号： C30B29/22 ,  C30B23/02 ,  H01L41/0815 ,  H01L41/1875 ,  H01L41/1878 ,  H01L41/319

    摘要： A perovskite-based thin film structure includes a semiconductor substrate layer, such as a crystalline silicon layer, having a top surface cut at an angle to the (001) crystal plane of the crystalline silicon. A perovskite seed layer is epitaxially grown on the top surface of the substrate layer. An overlayer of perovskite material is epitaxially grown above the seed layer. In some embodiments the perovskite overlayer is a piezoelectric layer grown to a thickness of at least 0.5 μm and having a substantially pure perovskite crystal structure, preferably substantially free of pyrochlore phase, resulting in large improvements in piezoelectric characteristics as compared to conventional thin film piezoelectric materials.

    摘要翻译： 钙钛矿型薄膜结构包括具有与晶体硅的（001）晶面成角度切割的顶表面的诸如晶体硅层的半导体衬底层。 在基底层的顶面上外延生长钙钛矿种子层。 在种子层上外延生长钙钛矿材料的覆层。 在一些实施方案中，钙钛矿覆盖层是生长至至少0.5μm厚度且具有基本上纯的钙钛矿晶体结构，优选基本上不含烧绿石相的压电层，与常规薄膜压电材料相比，导致压电特性的显着改善 。

    Corrosion resistant sealant for outer EBL of silicon-containing substrate and processes for preparing same
    93.
    发明申请
    Corrosion resistant sealant for outer EBL of silicon-containing substrate and processes for preparing same 审中-公开
    含硅基材外层EBL用耐腐蚀密封剂及其制备方法

    公开(公告)号：US20060280954A1

    公开(公告)日：2006-12-14

    申请号：US11150099

    申请日：2005-06-13

    申请人： Irene Spitsberg ,  Brian Hazel

    发明人： Irene Spitsberg ,  Brian Hazel

    IPC分类号： B32B13/04 ,  B32B9/00 ,  B32B19/00 ,  B05D5/12 ,  B05D1/36 ,  B05D3/02 ,  B05D1/08

    CPC分类号： C23C4/02 ,  C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  C23C4/18 ,  C23C28/042 ,  C23C28/048 ,  C23C28/322 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/36 ,  C04B41/0072 ,  C04B41/4558 ,  C04B41/5035 ,  C04B41/53 ,  C04B41/5037 ,  C04B41/4582 ,  C04B41/5024 ,  C04B41/4537 ,  C04B41/5031 ,  C04B41/4539 ,  C04B41/5032 ,  C04B41/522 ,  C04B41/4529 ,  C04B41/4527 ,  C04B41/5042 ,  C04B35/565 ,  C04B35/584 ,  C04B35/806

    摘要： An article comprising a silicon-containing substrate, an environmental barrier coating (EBC) overlying the substrate, wherein the EBC comprises a higher metal silicate-containing outer barrier layer; and a corrosion resistant alumina/aluminate sealant for the higher metal silicate-containing outer barrier layer. A process is also provided for forming a corrosion resistant alumina/aluminate sealant layer over the higher metal silicate-containing outer barrier layer. Also provided is an alternative process for treating a porous higher metal silicate-containing outer barrier layer with a liquid composition comprising an corrosion resistant alumina/aluminate sealant precursor to infiltrate the porous higher metal silicate-containing outer barrier layer with the alumina/aluminate sealant precursor in an amount sufficient to provide, when converted to the corrosion resistant alumina/aluminate sealant, protection of the environmental barrier coating against environmental attack; and converting the infiltrated alumina/aluminate sealant precursor within the porous higher metal silicate-containing outer barrier layer to the corrosion resistant alumina/aluminate sealant.

    摘要翻译： 一种制品，其包含含硅基材，覆盖所述基材的环境阻挡涂层（EBC），其中所述EBC包含较高含金属硅酸盐的外阻挡层; 和用于较高含金属硅酸盐的外阻挡层的耐腐蚀氧化铝/铝酸盐密封剂。 还提供了一种用于在高含金属硅酸盐的外阻挡层上形成耐腐蚀氧化铝/铝酸盐密封剂层的方法。 还提供了一种用含有耐腐蚀氧化铝/铝酸盐密封剂前体的液体组合物来处理含多孔的高含金属硅酸盐的外部阻隔层的替代方法，以用氧化铝/铝酸盐密封剂前体渗透含多孔的高含金属硅酸盐的外部阻隔层 其量足以提供，当转化为耐腐蚀的氧化铝/铝酸盐密封剂时，保护环境屏障涂层免受环境攻击; 并将渗透的含氧化铝/铝酸盐密封剂前体在含多孔高含金属硅酸盐的外阻挡层内转化成耐蚀氧化铝/铝酸盐密封剂。

    Diamond film-forming silicon and its manufacturing method
    95.
    发明申请
    Diamond film-forming silicon and its manufacturing method 审中-公开
    金刚石成膜硅及其制造方法

    公开(公告)号：US20060216514A1

    公开(公告)日：2006-09-28

    申请号：US10540640

    申请日：2003-12-24

    申请人： Hiroyuki Fujimura ,  Roberto Serikawa ,  Naoki Ishikawa ,  Takahiro Mishima

    发明人： Hiroyuki Fujimura ,  Roberto Serikawa ,  Naoki Ishikawa ,  Takahiro Mishima

    IPC分类号： C23C16/00 ,  B32B9/00 ,  B32B13/04

    CPC分类号： C30B25/18 ,  C23C16/27 ,  C23C16/545 ,  C30B25/02 ,  C30B29/04 ,  Y10T428/30

    摘要： The present invention intends to provide a diamond-coated silicon to be used in an industrially applicable diamond electrode. A diamond-coated silicon comprising a silicon substrate having a thickness of 500 μm or less is coated at least partially with electrically conductive diamond. The silicon substrate having a thickness of 500 μm or less is manufactured by the plate-like crystal growth process, and then the silicon substrate is coated with the electrically conductive diamond by the chemical vapor deposition process to manufacture the diamond-coated silicon. The diamond-coated silicon is flexible and can be stuck to an electrically conductive support substrate, and thereby a large area electrode and a three-dimensional electrode structure can be readily obtained.

    摘要翻译： 本发明旨在提供用于工业上应用的金刚石电极中的金刚石涂层的硅。 包含厚度为500μm或更小的硅衬底的金刚石涂覆的硅至少部分地涂覆有导电金刚石。 通过板状晶体生长工艺制造厚度为500μm或更小的硅衬底，然后通过化学气相沉积工艺用导电金刚石涂覆硅衬底，以制造金刚石涂覆的硅。 金刚石涂覆的硅是柔性的并且可以粘附到导电支撑衬底上，从而可以容易地获得大面积电极和三维电极结构。

    Reflectors, substrate processing apparatuses and methods for the same
    96.
    发明申请
    Reflectors, substrate processing apparatuses and methods for the same 审中-公开
    反射器，基板处理装置及其方法

    公开(公告)号：US20060196425A1

    公开(公告)日：2006-09-07

    申请号：US11350795

    申请日：2006-02-10

    申请人： Sung-Wook Hwang ,  Chul-Ho Shin

    发明人： Sung-Wook Hwang ,  Chul-Ho Shin

    IPC分类号： C23C16/00 ,  B32B13/04 ,  B32B9/00 ,  C23F1/00 ,  H01L21/306 ,  B32B15/04 ,  H05H1/24 ,  B32B19/00

    CPC分类号： H01J37/32633 ,  C23F4/00 ,  H01J37/32357

    摘要： A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.

    摘要翻译： 基板处理装置可以包括处理室，其包括布置在其上部区域中的等离子体产生单元。 栅格系统，其可以从由等离子体发生单元形成的等离子体提取离子，并且可以加速离子以具有基本均匀的方向性。 栅格系统可以位于等离子体生成单元的下方。 反射器可以布置在栅格系统下方，并且可以包括用于将从栅格系统加速的离子转换成中性光束的平行反射板。

    Manufacturing process for annealed wafer and annealed wafer
    98.
    发明申请
    Manufacturing process for annealed wafer and annealed wafer 审中-公开
    退火晶圆和退火晶圆的制造工艺

    公开(公告)号：US20060121291A1

    公开(公告)日：2006-06-08

    申请号：US11265129

    申请日：2005-11-03

    申请人： Yoshinori Hayamizu ,  Satoshi Tobe ,  Norihiro Kobayashi

    发明人： Yoshinori Hayamizu ,  Satoshi Tobe ,  Norihiro Kobayashi

    IPC分类号： B32B13/04 ,  H01L21/324

    CPC分类号： H01L21/3225

    摘要： There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.

    摘要翻译： 提供了即使在高温热处理下也能够抑制直径为300mm以上的CZ硅单晶晶片中的滑动产生的热处理方法，以消除在表面附近的生长缺陷 晶片，并且在晶片的表面层中具有DZ层的退火晶片，其氧化物以其高密度析出，其发挥高吸杂效应。 在由600℃〜1100℃的温度范围内进行利用切克劳斯基法（Czochralski method）拉伸的硅单晶锭制造的硅单晶晶片的第一次热处理，以在晶片本体中形成氧化物析出物， 此后，在1150〜1300℃的温度下进行第二次热处理。

    Nickel silicides formed by low-temperature annealing of compositionally modulated multilayers
    99.
    发明申请
    Nickel silicides formed by low-temperature annealing of compositionally modulated multilayers 审中-公开
    通过组成调制多层膜的低温退火形成的硅化镍

    公开(公告)号：US20060051596A1

    公开(公告)日：2006-03-09

    申请号：US10529311

    申请日：2003-09-26

    申请人： Jacob Jensen ,  David Johnson

    发明人： Jacob Jensen ,  David Johnson

    IPC分类号： B32B17/06 ,  B32B13/04 ,  B32B15/04 ,  C03C27/02

    CPC分类号： C03C17/36 ,  C03C17/3607 ,  C03C17/3636 ,  C03C17/3649 ,  C23C14/0682 ,  C23C14/14 ,  C23C14/5806 ,  C23C14/5893 ,  C23C26/00 ,  C23C28/021 ,  C23C28/023 ,  H01L21/28518 ,  H01L29/456 ,  Y10T428/12493 ,  Y10T428/12535 ,  Y10T428/12611

    摘要： Methods are disclosed for making a compound of nickel and silicon. According to an embodiment, on a surface of a substrate (e.g., silicon), multiple layer pairs are formed in a superposed manner. Each layer pair includes a respective layer of nickel and a respective layer of silicon each being 3 nm or less in thickness. The layers of nickel and silicon in the multiple layer pairs are formed in alternating order, thereby forming a multilayer structure, wherein the layers of nickel and silicon in the multilayer structure are formed at respective thicknesses corresponding to desired mole fractions of nickel and silicon in the multilayer structure. The multilayer structure is annealed at a temperature of 200° C. or less to form an amorphous alloy of nickel and silicon in the multilayer structure, wherein the alloy has the desired mole fractions of nickel and silicon. The amorphous alloy is allowed to nucleate and form a corresponding crystalline alloy having the desired mole fractions of nickel and silicon.

    摘要翻译： 公开了制造镍和硅化合物的方法。 根据一个实施例，在衬底（例如硅）的表面上，以叠加的方式形成多层对。 每个层对包括相应的镍层和相应的硅层，其厚度均为3nm或更小。 多层对中的镍和硅的层以交替的顺序形成，从而形成多层结构，其中多层结构中的镍和硅层分别以对应于镍和硅的所需摩尔分数的各自的厚度形成 多层结构。 多层结构在200℃或更低的温度下退火，以在多层结构中形成镍和硅的无定形合金，其中该合金具有所需的镍和硅的摩尔分数。 使非晶合金成核并形成具有所需的镍和硅的摩尔分数的相应的结晶合金。

    Process chamber and system for thinning a semiconductor workpiece
    100.
    发明申请
    Process chamber and system for thinning a semiconductor workpiece 审中-公开
    用于减薄半导体工件的处理室和系统

    公开(公告)号：US20060040111A1

    公开(公告)日：2006-02-23

    申请号：US10922762

    申请日：2004-08-20

    申请人： Kert Dolechek ,  Raymon Thompson

    发明人： Kert Dolechek ,  Raymon Thompson

    IPC分类号： B32B13/04 ,  B32B9/04

    CPC分类号： H01L21/6708 ,  H01L21/67126 ,  H01L21/67313 ,  H01L21/67754

    摘要： The present invention provides a system and method for processing batches of semiconductor wafers or workpieces. The system includes placing a batch of workpieces in a carrier that is loaded into a rotor assembly in a process chamber. The process chamber has a two spray manifolds with a dual inlet ports, and radially opposing vent and drain troughs extending from substantially a first end of a chamber body to substantially the second end of the chamber body. In the process chamber a variety of process fluids are sprayed on the workpieces to process the workpieces.

    摘要翻译： 本发明提供一种用于处理半导体晶片或工件批次的系统和方法。 该系统包括将一批工件放置在载入到处理室中的转子组件中的载体中。 处理室具有两个具有双入口端口的喷射歧管，以及径向相对的排气槽和排水槽，其从室主体的基本上的第一端延伸到室主体的基本上的第二端。 在处理室中，各种工艺流体喷涂在工件上以处理工件。