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    Counterfeiting deterrent and security devices, systems, and methods
    103.
    发明授权
    Counterfeiting deterrent and security devices, systems, and methods 有权
    假冒威慑和安全设备，系统和方法

    公开(公告)号：US09567682B2

    公开(公告)日：2017-02-14

    申请号：US15076490

    申请日：2016-03-21

    Applicant: Microfabrica Inc.

    Inventor： Gregory P. Schmitz ,  Michael S. Lockard ,  Ming-Ting Wu ,  Eric C. Miller ,  Adam L. Cohen

    IPC: G07F19/00 ,  C25D1/00 ,  B32B15/01 ,  C25D5/02 ,  C25D5/48 ,  B33Y10/00 ,  B33Y40/00 ,  B33Y70/00 ,  B33Y80/00

    CPC classification number: C25D1/003 ,  B32B15/01 ,  B33Y10/00 ,  B33Y40/00 ,  B33Y70/00 ,  B33Y80/00 ,  C25D1/08 ,  C25D5/022 ,  C25D5/48 ,  C25D7/005

    Abstract: A counterfeiting deterrent device according to one implementation of the disclosure includes a plurality of layers formed by an additive process. Each of the layers may have a thickness of less than 100 microns. At least one of the layers has a series of indentations formed in an outer edge of the layer such that the indentations can be observed to verify that the device originated from a predetermined source. According to another implementation, a counterfeiting deterrent device includes at least one raised layer having outer edges in the shape of a logo. A light source is configured and arranged to shine a light through a slit in a substrate layer of the device and past an intermediate layer to light up the outer edge of the raised layer. The layers of the device are formed by an additive process and have a thickness of less than 100 microns each.

    Abstract translation: 根据本公开的一个实施方式的防伪装置包括通过添加过程形成的多个层。 每个层可以具有小于100微米的厚度。 层中的至少一个具有形成在层的外边缘中的一系列凹痕，使得可以观察到凹痕以验证装置源自预定源。 根据另一个实施方案，一种防伪装置包括至少一个具有标志形状的外边缘的凸起层。 光源被配置和布置成将光照射穿过设备的基底层中的狭缝并且经过中间层以照亮凸起层的外边缘。 装置的层通过添加工艺形成，并且具有小于每个100微米的厚度。

    Cantilever Microprobes For Contacting Electronic Components
    104.
    发明申请
    Cantilever Microprobes For Contacting Electronic Components 审中-公开
    用于接触电子元件的悬臂式微机

    公开(公告)号：US20160109481A1

    公开(公告)日：2016-04-21

    申请号：US14927350

    申请日：2015-10-29

    Applicant: Microfabrica Inc.

    Inventor： Richard T. Chen ,  Ezekiel J. J. Kruglick ,  Christopher A. Bang ,  Dennis R. Smalley ,  Pavel B. Lembrikov

    IPC: G01R1/067 ,  G01R31/28

    Abstract: Embodiments disclosed herein are directed to compliant probe structures for making temporary or permanent contact with electronic circuits and the like. In particular, embodiments are directed to various designs of cantilever-like probe structures. Some embodiments are directed to methods for fabricating such probe or cantilever structures. In some embodiments, for example, cantilever probes have extended base structures, slide in mounting structures, multi-beam configurations, offset bonding locations to allow closer positioning of adjacent probes, compliant elements with tensional configurations, improved over travel, improved compliance, improved scrubbing capability, and/or the like.

    Abstract translation: 本文公开的实施例涉及用于与电子电路等进行临时或永久接触的柔性探针结构。 具体地，实施例涉及悬臂式探针结构的各种设计。 一些实施例涉及制造这种探针或悬臂结构的方法。 在一些实施例中，例如，悬臂探头具有延伸的基部结构，在安装结构中滑动，多光束配置，偏移粘合位置，以允许相邻探针，具有张力构型的柔顺元件，改善的行程，改善的顺应性，改进的擦洗 能力和/或类似物。

    Methods and Apparatus for Forming Multi-Layer Structures Using Adhered Masks
    105.
    发明申请
    Methods and Apparatus for Forming Multi-Layer Structures Using Adhered Masks 审中-公开
    使用粘附掩模形成多层结构的方法和装置

    公开(公告)号：US20140326607A1

    公开(公告)日：2014-11-06

    申请号：US14203409

    申请日：2014-03-10

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Jill R. Thomassian ,  Michael S. Lockard ,  Marvin M. Kilgo, III ,  Uri Frodis ,  Dennis R. Smalley

    IPC: C25D5/02

    CPC classification number: C25D1/003 ,  C25D1/00 ,  C25D1/20 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D5/14 ,  C25D5/48 ,  C25D5/50

    Abstract: Numerous electrochemical fabrication methods and apparatus are provided for producing multi-layer structures (e.g. having meso-scale or micro-scale features) from a plurality of layers of deposited materials using adhered masks (e.g. formed from liquid photoresist or dry film), where two or more materials may be provided per layer where at least one of the materials is a structural material and one or more of any other materials may be a sacrificial material which will be removed after formation of the structure. Materials may comprise conductive materials that are electrodeposited or deposited in an electroless manner. In some embodiments special care is undertaken to ensure alignment between patterns formed on successive layers.

    Abstract translation: 提供了多种电化学制造方法和装置，用于使用粘附的掩模（例如由液体光致抗蚀剂或干膜形成）从多层沉积材料制备多层结构（例如具有中尺度或微尺度特征），其中两个 或者可以在每层中提供更多的材料，其中至少一种材料是结构材料，并且任何其它材料中的一种或多种可以是在形成结构之后被去除的牺牲材料。 材料可以包括以无电解方式电沉积或沉积的导电材料。 在一些实施例中，特别注意确保在连续层上形成的图案之间的对准。

    Method and Apparatus for Maintaining Parallelism of Layers and/or Achieving Desired Thicknesses of Layers During the Electrochemical Fabrication of Structures
    106.
    发明申请
    Method and Apparatus for Maintaining Parallelism of Layers and/or Achieving Desired Thicknesses of Layers During the Electrochemical Fabrication of Structures 有权
    在电化学制造结构期间维持层的平行化和/或实现层的期望厚度的方法和装置

    公开(公告)号：US20140231263A1

    公开(公告)日：2014-08-21

    申请号：US14191061

    申请日：2014-02-26

    Applicant: MICROFABRICA INC.

    Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

    IPC: C25D5/48

    CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

    Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和用于在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测夹具，其相对于第一沉积层或相对于在制造过程期间形成的一些其它层，相对于衬底的初始表面确保沉积材料的精确高度。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机。

    Methods of reducing interlayer discontinuities in electrochemically fabricated three-dimensional structures
    107.
    发明申请
    Methods of reducing interlayer discontinuities in electrochemically fabricated three-dimensional structures 有权
    减少电化学制造的三维结构中的层间不连续性的方法

    公开(公告)号：US20040251142A1

    公开(公告)日：2004-12-16

    申请号：US10830262

    申请日：2004-04-21

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Dennis Smalley

    IPC: C25D005/02 ,  H01L021/00 ,  H01L021/84

    CPC classification number: C25D5/02 ,  B33Y10/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  H01P11/006

    Abstract: Disclosed methods reduce the discontinuities that between individual layers of a structure that is formed at least in part using electrochemical fabrication techniques. Discontinuities may exist between layers of a structure as a result of up-facing or down-facing regions defined in data descriptive of the structure or they may exist as a result of building limitations, e.g., those that result in non-parallel orientation between a building axis and sidewall surfaces of layers. Methods for reducing discontinuities may be applied to all regions or only to selected regions of the structure. Methods may be tailored to improve the accuracy between an original design of the structure and the structure as fabricated or they may simply be used to smooth the discontinuities between layers. Methods may include deposition operations that selectively favor filling of the discontinuities and/or etching operations that selectively favor removal of material from protrusions that define discontinuities.

    Abstract translation: 公开的方法减少了使用电化学制造技术至少部分形成的结构的各个层之间的不连续性。 结构的层之间可能存在不连续性，这是由于在描述结构的数据中定义的面向上或向下的区域的结果，或者它们可能由于构建限制而存在，例如导致在 建筑轴线和层的侧壁表面。 用于减少不连续性的方法可以应用于所有区域或仅应用于结构的选定区域。 可以调整方法以提高结构的原始设计和所制造的结构之间的精度，或者可以简单地用于平滑层之间的不连续性。 方法可以包括选择性地有利于填充不连续性和/或蚀刻操作的沉积操作，其选择性地有利于从限定不连续性的突起中去除材料。

    Multi-cell masks and methods and apparatus for using such masks to form three-dimensional structures
    108.
    发明申请
    Multi-cell masks and methods and apparatus for using such masks to form three-dimensional structures 失效
    多单元掩模以及使用这种掩模形成三维结构的方法和装置

    公开(公告)号：US20040134788A1

    公开(公告)日：2004-07-15

    申请号：US10677498

    申请日：2003-10-01

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Dennis R. Smalley ,  Gang Zhang

    IPC: C25D005/02 ,  C25D005/48

    CPC classification number: C25D5/022 ,  B33Y10/00 ,  C25D1/08 ,  C25D5/10

    Abstract: Multilayer structures are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. Selectivity of deposition is obtained via a multi-cell controllable mask. Alternatively, net selective deposition is obtained via a blanket deposition and a selective removal of material via a multi-cell mask. Individual cells of the mask may contain electrodes comprising depositable material or electrodes capable of receiving etched material from a substrate. Alternatively, individual cells may include passages that allow or inhibit ion flow between a substrate and an external electrode and that include electrodes or other control elements that can be used to selectively allow or inhibit ion flow and thus inhibit significant deposition or etching. Single cell masks having a cell size that is smaller or equal to the desired deposition resolution may also be used to form structures.

    Abstract translation: 多层结构通过在多个覆盖层和粘附层中的一种或多种材料的沉积进行电化学制造。 沉积的选择性通过多单元可控掩模获得。 或者，通过覆盖沉积和通过多细胞掩模选择性去除材料获得净选择性沉积。 掩模的各个单元可以包含包含可沉积材料的电极或能够从基底接受蚀刻材料的电极。 或者，单个电池可以包括允许或抑制衬底和外部电极之间的离子流动并且包括电极或其它控制元件的通道，其可以用于选择性地允许或抑制离子流动，从而抑制显着的沉积或蚀刻。 具有小于或等于所需沉积分辨率的单元尺寸的单细胞掩模也可用于形成结构。

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