公开(公告)号：US20090160595A1

公开(公告)日：2009-06-25

申请号：US12391251

申请日：2009-02-23

Applicant: Tao Feng ,  Xiaolian Zhang ,  Francois Hebert ,  Ming Sun

Inventor： Tao Feng ,  Xiaolian Zhang ,  Francois Hebert ,  Ming Sun

IPC: H01F5/00 ,  H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49861 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L21/4832 ,  H01L21/563 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

Abstract translation: 公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。 底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。 功率电感器具有闭合磁环的电感芯。 电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。 由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈， 共同形成围绕电感器芯的感应线圈。 顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。

公开(公告)号：US20090134503A1

公开(公告)日：2009-05-28

申请号：US11986673

申请日：2007-11-23

Applicant: Tao Feng ,  Xiaotian Zhang ,  Francois Hebert

Inventor： Tao Feng ,  Xiaotian Zhang ,  Francois Hebert

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/495 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.

Abstract translation: 公开了一种具有引线框架的集成电感器的半导体功率器件封装。 半导体功率器件封装包括具有多个引线的引线框架，附接到引线框架的电感器芯，使得多个引线端通过形成在电感器芯中的窗体露出，多个接合线， 多个接合线将多个引线端中的每一个连接到围绕电感器芯的相邻引线以形成电感器，以及耦合到电感器的功率集成电路。 在替代实施例中，顶部引线框架通过连接芯片将多个引线端中的每一个耦合到围绕电感器芯的相邻引线。

公开(公告)号：US20080173969A1

公开(公告)日：2008-07-24

申请号：US11656104

申请日：2007-01-22

Applicant: Francois Hebert ,  Tao Feng

Inventor： Francois Hebert ,  Tao Feng

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/861 ,  H01L29/872

Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Abstract translation: 本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。 所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛 用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

公开(公告)号：US20080067584A1

公开(公告)日：2008-03-20

申请号：US11522669

申请日：2006-09-17

Applicant: Sik K Lui ,  Francois Hebert ,  Anup Bhalla

Inventor： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Abstract translation: 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US07342433B2

公开(公告)日：2008-03-11

申请号：US11270062

申请日：2005-11-08

Applicant: Richard A. Harris ,  Francois Hebert

Inventor： Richard A. Harris ,  Francois Hebert

IPC: H03K17/687

CPC classification number: H01L27/0266 ,  H02H5/042 ,  H02H5/044 ,  H02H9/025 ,  H02H9/046

Abstract: An apparatus and method for enhanced transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device such that the p- and n-channel devices mutually switch off to block the transient. The apparatus has an enhancer circuit for applying an enhancement bias to a gate terminal of at least one of the depletion mode n-channel devices of the TBU to reduce a total resistance Rtot of the apparatus. Alternatively, the apparatus has an enhancement mode NMOS transistor and a TBU connected thereto to help provide an enhancement bias to a gate terminal of the enhancement mode NMOS.

Abstract translation: 一种用于增强瞬态阻塞的装置和方法，其采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）。 执行互连，使得瞬态改变p沟道器件的偏置电压V P和N沟道器件的偏置电压V N n N，使得p - 和n通道设备相互关闭以阻止瞬态。 该装置具有增强器电路，用于向TBU中的至少一个耗尽型n沟道器件的栅极端子施加增强偏置，以减小器件的总电阻R tht。 或者，该装置具有增强型NMOS晶体管和与其连接的TBU，以帮助向增强型NMOS的栅极端提供增强偏置。

公开(公告)号：US20080023785A1

公开(公告)日：2008-01-31

申请号：US11495803

申请日：2006-07-28

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L23/58 ,  H01L21/336

CPC classification number: H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Abstract translation: 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US20080006951A1

公开(公告)日：2008-01-10

申请号：US11444977

申请日：2006-05-31

Applicant: Francois Hebert ,  Anup Bhalla

Inventor： Francois Hebert ,  Anup Bhalla

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract translation: 公开了一种铜键合兼容的键合焊盘结构及其相关方法。 器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

公开(公告)号：US20070012983A1

公开(公告)日：2007-01-18

申请号：US11487142

申请日：2006-07-14

Applicant: Robert Yang ,  Richard Blanchard ,  Francois Hebert

Inventor： Robert Yang ,  Richard Blanchard ,  Francois Hebert

IPC: H01L29/94

CPC classification number: H01L29/7803 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.

Abstract translation: 本发明涉及在半导体器件中实现高击穿电压和低导通电阻，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部区域，中间区域和底部区域。 该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。 具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质 区域，使得击穿电压V BAT最大化，导通电阻最小化。 可以采用设置在第二绝缘沟槽中的第二串联电容结构来终止该器件。

公开(公告)号：US20060238936A1

公开(公告)日：2006-10-26

申请号：US11410575

申请日：2006-04-24

Applicant: Richard Blanchard ,  Richard Harris ,  Francois Hebert

Inventor： Richard Blanchard ,  Richard Harris ,  Francois Hebert

IPC: H02H9/00

CPC classification number: H01J1/72 ,  C09K11/59 ,  H01H9/548 ,  H02H9/025

Abstract: An apparatus and a method for uni-directional and bi-directional transient blocking. The uni-directional apparatus has a depletion mode n-channel device at its input and a normally closed relay, e.g., a micro-electro-mechanical (MEM) relay, interconnected with the depletion mode n-channel device and the input in such a way that at a predetermined current value the transient causes the normally closed relay to switch into an open state and apply a bias voltage Vn on the depletion mode n-channel device that is sufficiently high to switch it “off” thus block the transient. An analogous arrangement at the output taking advantage of the same or a second relay renders the apparatus bi-directional. The structure of the apparatus and the method of operation ensure a reliable and repeatable trip current Itrip and render the apparatus very robust and feasible for low-cost manufacture.

Abstract translation: 一种用于单向和双向瞬态阻塞的装置和方法。 单向设备在其输入端具有耗尽模式n沟道器件和常闭继电器，例如与耗尽型n沟道器件互连的微机电（MEM）继电器，以及在这种 在预定电流值下，瞬态使常闭继电器切换到打开状态，并在足够高以切换它的耗尽型n沟道器件上施加偏置电压V N“ 关闭“从而阻止瞬态。 利用相同或第二中继器在输出端处的类似布置使设备双向。 该装置的结构和操作方法确保了可靠且可重复的跳闸电流跳闸，并且使得该装置非常坚固且可用于低成本制造。

公开(公告)号：US20060098373A1

公开(公告)日：2006-05-11

申请号：US11130793

申请日：2005-05-17

Applicant: Francois Hebert ,  Richard Harris

Inventor： Francois Hebert ,  Richard Harris

IPC: H02H9/06

CPC classification number: H01L27/0266 ,  H01L21/823462 ,  H01L27/088 ,  H02H9/025 ,  H02H9/046

Abstract: A TBU system that includes a TBU combined with control and monitoring features. For example, in one embodiment, TBU elements are combined with a status indication switch or indicator. In another embodiment, TBU elements are combined with event logging for over voltage conditions, over current conditions, including an indication of when the event occurred and an amount of energy that was let through.

Abstract translation: 一个TBU系统，包括TBU与控制和监控功能相结合。 例如，在一个实施例中，TBU元件与状态指示开关或指示器组合。 在另一个实施例中，TBU元件与过电压条件的事件记录相结合，包括当前状况的发生以及通过的能量的指示。