公开(公告)号：US20090160595A1

公开(公告)日：2009-06-25

申请号：US12391251

申请日：2009-02-23

申请人： Tao Feng ,  Xiaolian Zhang ,  Francois Hebert ,  Ming Sun

发明人： Tao Feng ,  Xiaolian Zhang ,  Francois Hebert ,  Ming Sun

IPC分类号： H01F5/00 ,  H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49861 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L21/4832 ,  H01L21/563 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

摘要翻译： 公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。 底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。 功率电感器具有闭合磁环的电感芯。 电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。 由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈， 共同形成围绕电感器芯的感应线圈。 顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。

公开(公告)号：US20090160045A1

公开(公告)日：2009-06-25

申请号：US11963690

申请日：2007-12-21

申请人： Ming Sun ,  Tao Feng ,  Francois Hebert ,  Yueh-Se Ho

发明人： Ming Sun ,  Tao Feng ,  Francois Hebert ,  Yueh-Se Ho

IPC分类号： H01L23/06 ,  H01L21/304

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/02 ,  H01L24/11 ,  H01L24/17 ,  H01L2221/68354 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

摘要翻译： 公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。 将包含多个半导体芯片的晶片安装在封装基板上。 多个半导体芯片包括暴露背面的一个或多个电极。 去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。 将导电材料施加到半导体芯片的背面和间隙中。 然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。 结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

公开(公告)号：US20090194880A1

公开(公告)日：2009-08-06

申请号：US12023921

申请日：2008-01-31

申请人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L23/48 ,  H01L21/304

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，方便用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US20090167477A1

公开(公告)日：2009-07-02

申请号：US12397473

申请日：2009-03-04

申请人： Tao Feng ,  Xiaotian Zhang ,  Francois Hebert ,  Ming Sun

发明人： Tao Feng ,  Xiaotian Zhang ,  Francois Hebert ,  Ming Sun

IPC分类号： H01F5/00 ,  H01F41/00

CPC分类号： H01L23/495 ,  H01F3/14 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/2828 ,  H01F2027/2814 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49073 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.

摘要翻译： 公开了感应电力电子封装。 它有一个电路基板，带有功率电感器。 功率电感器具有具有内部窗口的闭合磁环的电感器芯。 封闭的磁环可以包括用于电感调节的气隙。 电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。 还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。 内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。 外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。 功率集成电路也可以连接到电路基板的顶侧。

公开(公告)号：US20080242052A1

公开(公告)日：2008-10-02

申请号：US11694888

申请日：2007-03-30

申请人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L21/30

CPC分类号： H01L21/3043 ,  H01L21/78

摘要： A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes: Thinning wafer central portion from its back-side to produce a thin region while preserving original wafer thickness in the wafer periphery for structural strength. Forming ohmic contact at wafer back-side. Separating and collecting pre-fabricated devices. This further includes: Releasably bonding wafer back-side onto single-sided dicing tape, in turn supported by a dicing frame. Providing a backing plate to match the thinned out wafer central portion. Sandwiching the dicing tape between wafer and backing plate then pressing the dicing tape to bond with the wafer. With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.

摘要翻译： 公开了制造薄半导体器件的方法。 从具有预制的前端器件的晶片开始，该方法包括：从其背面将晶片中心部分变薄以产生薄区域，同时在晶片周边保留原始晶片厚度以获得结构强度。 在晶圆背面形成欧姆接触。 分离和收集预制设备。 这还包括：将晶片背面可释放地粘合到单面切割胶带上，然后由切割架支撑。 提供背板以匹配变薄的晶片中心部分。 将切割胶带夹在晶片和背板之间，然后按压切割胶带与晶片结合。 利用阶梯型卡盘来支撑晶片背面，在一个切割操作中，预制的装置彼此分离并且与晶片周边分离，切割深度比晶片中心部分稍厚。 然后拾取并收集分离的薄半导体器件。

公开(公告)号：US20090057869A1

公开(公告)日：2009-03-05

申请号：US11849160

申请日：2007-08-31

申请人： Francois Hebert ,  Xiaotian Zhang ,  Kai Liu ,  Ming Sun ,  Anup Bhalla

发明人： Francois Hebert ,  Xiaotian Zhang ,  Kai Liu ,  Ming Sun ,  Anup Bhalla

IPC分类号： H01L23/52

CPC分类号： H01L24/41 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L25/072 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01055 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/37099 ,  H01L2924/206

摘要： A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.

摘要翻译： 公开了电路封装组件。 组件包括导电基板; 具有在与导电基板的表面相对并与其电接触的一侧具有源极的高边n沟道金属氧化物半导体场效应晶体管（NMOSFET）和低侧标准n沟道金属氧化物半导体场效应晶体管（ NMOSFET），其在面向导电基板的一侧具有漏极并与其电接触。 与传统封装相比，以这种方式共同封装高边和低边NMOSFET可以减小封装尺寸和寄生电感和电容。

公开(公告)号：US20080238599A1

公开(公告)日：2008-10-02

申请号：US11729311

申请日：2007-03-27

申请人： Francois Hebert ,  Ming Sun

发明人： Francois Hebert ,  Ming Sun

IPC分类号： H01F17/04 ,  H01F27/28

CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/1902 ,  H01L2924/3025 ,  Y10T29/4902 ,  Y10T29/49075 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

摘要翻译： 公开了一种具有电感器基板和翻转到电感器基板上的功率集成电路的芯片级功率转换器封装。 电感器基板包括其上形成有平面螺旋电感器的高电阻率基板。

公开(公告)号：US20090108456A1

公开(公告)日：2009-04-30

申请号：US11932845

申请日：2007-10-31

申请人： Francois Hebert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： Francois Hebert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US20080180871A1

公开(公告)日：2008-07-31

申请号：US11657862

申请日：2007-01-25

申请人： Francois Hebert ,  Ming Sun

发明人： Francois Hebert ,  Ming Sun

IPC分类号： H02H5/04 ,  H01L21/60

CPC分类号： H01L25/18 ,  H01L23/62 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

摘要翻译： 可复位的过流自保护半导体功率器件包括垂直功率半导体芯片和由诸如PTC材料的限流材料构成的过电流保护层。 过电流保护层可以夹在垂直功率半导体芯片和导电板之间，该导电板可以是装置安装在其上的引线框，金属板，PCB板或PCB。

公开(公告)号：US07868431B2

公开(公告)日：2011-01-11

申请号：US12391251

申请日：2009-02-23

申请人： Tao Feng ,  Xiaotian Zhang ,  François Hébert ,  Ming Sun

发明人： Tao Feng ,  Xiaotian Zhang ,  François Hébert ,  Ming Sun

IPC分类号： H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01F5/00

CPC分类号： H01L23/49861 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L21/4832 ,  H01L21/563 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

摘要翻译： 公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。 底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。 功率电感器具有闭合磁环的电感芯。 电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。 由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈， 共同形成围绕电感器芯的感应线圈。 顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。