公开(公告)号：US09735242B2

公开(公告)日：2017-08-15

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

公开(公告)号：US09735061B1

公开(公告)日：2017-08-15

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min-gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC: H01L21/44 ,  H01L21/31 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US09722053B1

公开(公告)日：2017-08-01

申请号：US15075557

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US20170207122A1

公开(公告)日：2017-07-20

申请号：US15470006

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.

公开(公告)号：US09502286B2

公开(公告)日：2016-11-22

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09478538B1

公开(公告)日：2016-10-25

申请号：US14820661

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L27/088 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。

公开(公告)号：US09425106B1

公开(公告)日：2016-08-23

申请号：US14674108

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins above a substrate. At least one dielectric material is formed above and between the plurality of fins. A mask layer is formed above the dielectric material. The mask layer has an opening defined therein. A portion of the at least one dielectric material exposed by the opening is removed to expose top and sidewall surface portions of at least a subset of the fins. An etching process is performed to remove the portions of the fins in the subset exposed by removing the portion of the at least one dielectric material.

Abstract translation: 一种方法包括在衬底上形成多个翅片。 在多个翅片之上和之间形成至少一个电介质材料。 在电介质材料上形成掩模层。 掩模层具有限定在其中的开口。 去除由开口暴露的至少一个电介质材料的一部分，以暴露散热片的至少一个子集的顶部和侧壁表面部分。 执行蚀刻工艺以去除通过去除至少一种电介质材料的部分而暴露的子集中的散热片的部分。

公开(公告)号：US20160204034A1

公开(公告)日：2016-07-14

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09379017B1

公开(公告)日：2016-06-28

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09362279B1

公开(公告)日：2016-06-07

申请号：US14609171

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andy Wei ,  William James Taylor ,  Ryan Ryoung-han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material. The resulting structure has replacement (conductive) gates, conductive material above the N and P type epitaxy, and a contact to the conductive material for each of N and P type epitaxy.

Abstract translation: 公开了接触形成方法和结构。 该方法包括提供起始半导体结构，该结构包括具有耦合到基板的翅片的半导体基板，翅片的底部被第一介电层包围，覆盖每个翅片的一部分的虚拟栅极，间隔件和 每个虚拟栅极的盖，以及延伸到第一介电层并暴露第一介电层的栅极之间的衬里沟槽。 该方法还包括在沟槽中的相邻散热片之间产生硬掩模材料的外延屏障，在邻近屏障相对侧的鳍片上产生N和P型外延材料，并在N和P型外延材料上产生牺牲半导体外延， 使得随后的去除可以对N型和P型外延材料选择性地进行。 所得结构具有替代（导电）栅极，N和P型外延上方的导电材料，以及N和P型外延中的每一个与导电材料的接触。