公开(公告)号：US09564447B1

公开(公告)日：2017-02-07

申请号：US14842345

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Ajey P. Jacob ,  Min-hwa Chi

IPC: H01L27/112 ,  G11C13/00

CPC classification number: H01L27/11206 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/008 ,  H01L23/5256 ,  H01L23/53276 ,  H01L27/112 ,  H01L29/0676 ,  H01L29/413

Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.

Abstract translation: 提供了可编程器件制造的方法和结构。 制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。 可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

公开(公告)号：US09543298B1

公开(公告)日：2017-01-10

申请号：US15067455

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0273 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of forming a single diffusion break includes etching rows of fins into a substrate of a structure from a patterned fin hardmask, the remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the structure to expose the fin hardmask. A photoresist layer is disposed over the structure. An isolation region is patterned across the fins to form first and second parallel fin arrays, wherein any remaining photoresist layer has self-aligned edges which are self-aligned with the isolation region. The self-aligned edges are trimmed to expose end portions of the fin hardmask. The exposed end portions are removed. The remaining photoresist layer is removed. A second dielectric fill material is disposed and planarized over the structure to form a base for a single diffusion break (SDB) in the isolation region.

Abstract translation: 形成单个扩散断裂的方法包括从图案化散热片硬掩模将排成一排散热片蚀刻成结构的基板，剩余的散热片硬掩模与散热片自对准。 在结构上设置和平坦化第一介电填充材料以暴露散热片硬掩模。 光致抗蚀剂层设置在结构上。 隔离区跨越翅片形成图案以形成第一和第二平行翅片阵列，其中任何残留的光致抗蚀剂层具有与隔离区自对准的自对准边缘。 自对准边缘被修剪以暴露散热片硬掩模的端部。 露出的端部被去除。 去除剩余的光致抗蚀剂层。 第二介电填充材料在结构上设置和平坦化，以形成隔离区域中的单个扩散断裂（SDB）的基底。

公开(公告)号：US09312145B2

公开(公告)日：2016-04-12

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L21/469 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US09299608B2

公开(公告)日：2016-03-29

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US20150287727A1

公开(公告)日：2015-10-08

申请号：US14742537

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/16 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

公开(公告)号：US09064888B2

公开(公告)日：2015-06-23

申请号：US13931211

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

Abstract: Methods for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency and the resulting devices are disclosed. Embodiments may include designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the substrate corresponding to the source region, and forming a tunneling field-effect transistor incorporating the source region and the drain region.

Abstract translation: 公开了用于形成TFET的源极或源极和漏极中的堆垛层错以提高隧道效率的方法以及所得到的器件。 实施例可以包括指定衬底内的区域，其随后将对应于源极区域和漏极区域，在对应于源极区域的衬底内选择性地形成堆垛层错，以及形成结合源区域和漏极的隧道场效应晶体管 地区。

公开(公告)号：US20150126008A1

公开(公告)日：2015-05-07

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US08946029B2

公开(公告)日：2015-02-03

申请号：US13674142

申请日：2012-11-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L21/823821

Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure.

Abstract translation: 公开了具有外延形成的源极和漏极区域的FinFET结构的半导体集成电路的制造方法。 例如，制造集成电路的方法包括在半导体衬底上形成多个硅鳍结构，在翅片结构的垂直侧壁上形成一次性间隔物，并在氧化硅材料上方并在一次性衬垫上方沉积氧化硅材料。 该方法还包括在至少一个翅片结构的侧壁上各向异性地蚀刻翅片结构和一次性间隔物中的至少一个，从而在氧化硅材料中留下空隙，并从中将氧化硅材料和一次性间隔件从 至少另一个翅片结构，同时留下至少一个其它鳍状结构未蚀刻。 此外，该方法包括在空隙中和未蚀刻的鳍结构上外延生长硅材料。 在空隙中形成未合并的源极/漏极区，并且在未蚀刻的鳍结构上形成合并的源极/漏极区。

公开(公告)号：US08906768B2

公开(公告)日：2014-12-09

申请号：US13840692

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7848

Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.

Abstract translation: 为了在限定在FINFET半导体结构的鳍上的一个或多个源极和漏极上形成应力源，可以采用一种方法，包括在鳍上限定的一个或多个源极和漏极上执行选择性外延生长（SEG） 在源极和漏极中的一个或多个处将散热片与体硅衬底分离开，并且在源极和漏极之一上进一步执行SEG，以形成围绕外延生长应力的环绕，该外延生长应力应力连接源极和漏极的沟道。 形成的应力器可以形成为使得限定缠绕结构的外延生长材料连接到本体基板。 所形成的应力源可以增加连接限定的源极和漏极的通道中的迁移率。

公开(公告)号：US08674413B1

公开(公告)日：2014-03-18

申请号：US13670605

申请日：2012-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi

IPC: H01L29/76

CPC classification number: H01L21/823821 ,  H01L27/0924

Abstract: One illustrative device disclosed herein includes a substantially un-doped layer of a semiconductor material positioned above a semiconducting substrate, a device isolation structure, at least a portion of which is positioned in a trench that extends through the substantially un-doped semiconductor material and into the substrate, a plurality of outer fins and at least one inner fin defined in the substantially un-doped layer of semiconductor material, wherein the at least one inner fin is positioned laterally between the plurality of outer fins and wherein a width of a bottom of each of the plurality of outer fins is greater than a width of a bottom of the inner fin, and a gate electrode positioned around at least a portion of the plurality of outer fins and the inner fin.

Abstract translation: 本文公开的一个示例性器件包括位于半导体衬底上方的半导体材料的基本上未掺杂的层，器件隔离结构，其至少一部分位于延伸穿过基本上未掺杂的半导体材料的沟槽中并且形成 基板，多个外部散热片和至少一个内部翅片，其限定在半导体材料的基本上未掺杂的层中，其中所述至少一个内部翅片横向地定位在所述多个外部翅片之间，并且其中底部的宽度 所述多个外翅片中的每一个大于所述内翅片的底部的宽度，以及位于所述多个外翅片和所述内翅片的至少一部分周围的栅电极。