公开(公告)号：US12009226B2

公开(公告)日：2024-06-11

申请号：US17458663

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/2101 ,  H01L2924/37001

Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

公开(公告)号：US20240079235A1

公开(公告)日：2024-03-07

申请号：US18500593

申请日：2023-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hsing-Chieh Lee ,  Ming-Tan Lee

IPC: H01L21/027 ,  G03F7/038 ,  G03F7/039 ,  G03F7/075 ,  G03F7/09 ,  G03F7/42

CPC classification number: H01L21/0276 ,  G03F7/0382 ,  G03F7/0392 ,  G03F7/0758 ,  G03F7/091 ,  G03F7/427

Abstract: A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti -reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.

公开(公告)号：US11923207B2

公开(公告)日：2024-03-05

申请号：US18308909

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/49 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49822 ,  H01L24/13 ,  H01L21/568 ,  H01L2221/68331 ,  H01L2224/10122 ,  H01L2924/19106

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

公开(公告)号：US11842955B2

公开(公告)日：2023-12-12

申请号：US17852766

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzung-Hui Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48 ,  H01L23/485 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/485 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

公开(公告)号：US11842896B2

公开(公告)日：2023-12-12

申请号：US17869591

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hsing-Chieh Lee ,  Ming-Tan Lee

IPC: G03F7/09 ,  G03F7/038 ,  G03F7/039 ,  H01L21/027 ,  G03F7/42 ,  G03F7/075

CPC classification number: H01L21/0276 ,  G03F7/0382 ,  G03F7/0392 ,  G03F7/0758 ,  G03F7/091 ,  G03F7/427

Abstract: A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti-reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.

公开(公告)号：US20230377969A1

公开(公告)日：2023-11-23

申请号：US18362083

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L24/09 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76873 ,  H01L23/3171 ,  H01L21/563 ,  H01L23/5329 ,  H01L21/76885 ,  H01L2224/02373 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US20230369153A1

公开(公告)日：2023-11-16

申请号：US18361300

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Tai-Min Chang ,  Hui-Jung Tsai ,  De-Yuan Lu ,  Ming-Tan Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L23/3114 ,  H01L21/561 ,  H01L24/03 ,  H01L23/481 ,  H01L2224/0233

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

公开(公告)号：US11817399B2

公开(公告)日：2023-11-14

申请号：US17340036

申请日：2021-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zi-Jheng Liu ,  Jo-Lin Lan ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L23/58 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/585 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5386 ,  H01L23/564 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/5446 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.

公开(公告)号：US20230307251A1

公开(公告)日：2023-09-28

申请号：US18324686

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2225/06568

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US20230274976A1

公开(公告)日：2023-08-31

申请号：US18302545

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/76871 ,  H01L21/32139 ,  H01L21/565 ,  H01L21/76856 ,  H01L23/3107 ,  H01L23/53238 ,  H01L24/09 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L23/5226 ,  H01L2224/02379

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.