公开(公告)号：US09293330B2

公开(公告)日：2016-03-22

申请号：US14011832

申请日：2013-08-28

申请人： Infineon Technologies AG

发明人： Hans-Joachim Schulze ,  Ingo Muri ,  Friedrich Kroener ,  Werner Schustereder

IPC分类号： H01L21/322 ,  H01L29/868 ,  H01L21/265 ,  H01L21/263 ,  H01L21/324 ,  H01L21/3063

CPC分类号： H01L21/26513 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3063 ,  H01L21/3242

摘要： A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

摘要翻译： 公开了一种制造半导体的方法，该方法具有：提供具有第一面和第二面的半导体本体; 通过所述半导体本体中的所述第一侧至所述半导体本体的第一深度位置的第一注入而在所述半导体本体中形成n掺杂区; 以及通过所述半导体本体中的所述第二侧到所述半导体本体的第二深度位置的第二注入在所述半导体本体中形成p掺杂区，在所述n掺杂区和所述p掺杂区之间形成pn结 在半导体体内。

公开(公告)号：US09244019B2

公开(公告)日：2016-01-26

申请号：US13547763

申请日：2012-07-12

申请人： Patrick Reynaud ,  Christophe Gourdel

发明人： Patrick Reynaud ,  Christophe Gourdel

IPC分类号： C30B33/02 ,  G01N21/95 ,  H01L21/66 ,  H01L21/265 ,  H01L21/322 ,  G01N1/28 ,  G01N21/47

CPC分类号： G01N21/9501 ,  G01N1/28 ,  G01N21/4795 ,  H01L21/26533 ,  H01L21/3226 ,  H01L22/12 ,  H01L22/24

摘要： A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750° C. and 850° C. for a time period of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900° C. and 1000° C. for a time period of between 1 hour and 10 hour hours to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.

摘要翻译： 一种用于测量通过硅锭拉制获得的硅衬底中的缺陷的方法，其中所述缺陷具有小于20nm的尺寸。 该方法包括在750℃和850℃之间的温度下对基材进行第一次缺陷固结热处理，时间为30分钟至1小时，以巩固缺陷; 在900℃至1000℃之间的温度下对基材进行第二次缺陷放大热处理1小时至10小时的时间，将缺陷扩大至大于或等于20的尺寸 nm，含有氧沉淀物的扩大缺陷; 测量衬底的表面层中增大的缺陷的尺寸和密度; 并且基于扩大缺陷的测量来计算缺陷的初始尺寸。

公开(公告)号：US20160005623A1

公开(公告)日：2016-01-07

申请号：US14653580

申请日：2013-12-19

申请人： Prised Solar Inc.

发明人： Wahid Shams-Kolahi ,  Harry Ruda ,  Christina F Souza

IPC分类号： H01L21/322

CPC分类号： H01L21/3221 ,  B01J19/12 ,  C30B13/24 ,  C30B29/06 ,  H01L21/3228 ,  H01L31/186 ,  Y02E10/50 ,  Y02P70/521

摘要： The present disclosure provides a method for upgrading materials, for example crystalline metallurgical silicon, to remove impurities using microwave processing to induce migration of impurities in the material to one or both of internal surfaces where they are trapped and neutralized or one or more external surfaces followed by trapping of the impurity by binding to gettering agents on the surface with subsequent removal of the impurity and gettering agent.

摘要翻译： 本公开提供了一种用于升级材料的方法，例如晶体冶金硅，以使用微波加工来移除杂质以诱导材料中的杂质迁移到其中被捕获和中和的一个或两个内表面，或者一个或多个外表面被跟随 通过在表面上与吸附剂结合而捕获杂质，随后除去杂质和吸杂剂。

公开(公告)号：US09230810B2

公开(公告)日：2016-01-05

申请号：US12873147

申请日：2010-08-31

申请人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

发明人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC分类号： H01L21/322 ,  H01L21/20 ,  H01L21/22 ,  H01L29/78

CPC分类号： H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

摘要： Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

摘要翻译： 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US09224601B2

公开(公告)日：2015-12-29

申请号：US14078217

申请日：2013-11-12

申请人： SUMCO Corporation

发明人： Takeshi Kadono

IPC分类号： H01L21/02 ,  H01L27/146 ,  H01L21/265 ,  H01L21/322

CPC分类号： H01L21/26566 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/3221 ,  H01L21/3225 ,  H01L27/14687

摘要： Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. A method of producing an epitaxial silicon wafer includes a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions to form a modifying layer formed from a constituent element of the cluster ions in a surface portion of the silicon wafer; and a second step of forming an epitaxial layer on the modifying layer of the silicon wafer.

摘要翻译： 提供了一种外延硅晶片，其由位错簇引起的外延缺陷和通过较高的吸杂能力实现的具有减少的金属污染的COP和一种制造外延晶片的方法。 一种外延硅晶片的制造方法，其特征在于，包括：第一工序，在硅晶片的表面部照射不含位错簇的硅晶片和具有簇离子的COP，形成由所述簇离子的构成元素形成的改性层; 以及在硅晶片的改性层上形成外延层的第二步骤。

公开(公告)号：US09214424B2

公开(公告)日：2015-12-15

申请号：US13452044

申请日：2012-04-20

申请人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

发明人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L23/522 ,  H01L21/311 ,  H01L21/322 ,  H01L21/74 ,  H01L21/3115 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/44 ,  H01L21/743 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

摘要翻译： 公开了一种用于制造半导体部件的圆形导线的方法。 在该方法中，提供部分完成的半导体部件。 部分完成的半导体部件具有在垂直方向上与底侧间隔开的底侧和顶侧。 还提供了一种蚀刻剂。 在顶侧设置介电层。 介电层具有至少两个不同的区域，当蚀刻剂用蚀刻剂蚀刻时，其表现出不同的蚀刻速率。 随后，在电介质层中形成沟槽，使得沟槽与不同区域中的每一个相交。 然后，通过用不同蚀刻速率的蚀刻剂蚀刻沟槽来加宽沟槽。 通过用导电材料填充加宽的沟槽，形成导体线。

公开(公告)号：US20150357508A1

公开(公告)日：2015-12-10

申请号：US14655366

申请日：2013-12-18

申请人： MERCK PATENT GMBH

发明人： Ingo KOEHLER ,  Oliver DOLL ,  Sebastian BARTH

IPC分类号： H01L31/18 ,  H01L21/02 ,  H01L21/322

CPC分类号： H01L31/186 ,  C30B29/06 ,  C30B31/00 ,  H01L21/02112 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/2225 ,  H01L21/2255 ,  H01L21/3221 ,  H01L31/02167 ,  H01L31/02363 ,  H01L31/0288 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention relates to a novel process for the preparation of printable, low- to high-viscosity oxide media, and to the use thereof in the production of solar cells.

摘要翻译： 本发明涉及一种制备可印刷的低至高粘度氧化物介质的新方法及其在太阳能电池生产中的应用。

公开(公告)号：US20150348773A1

公开(公告)日：2015-12-03

申请号：US14410790

申请日：2013-07-01

申请人： Applied Materials, Inc.

发明人： Mingwei ZHU ,  Nag B. PATIBANDLA ,  Rongjun WANG ,  Vivek AGRAWAL ,  Anantha SUBRAMANI ,  Daniel Lee DIEHL ,  Xianmin TANG

IPC分类号： H01L21/02 ,  H01L21/322 ,  H01J37/34 ,  H01L21/3065

CPC分类号： H01L21/0254 ,  C23C14/0036 ,  C23C14/0641 ,  H01J37/3426 ,  H01J37/3467 ,  H01L21/02458 ,  H01L21/02631 ,  H01L21/3065 ,  H01L21/3228

摘要： Embodiments of the invention described herein generally relate to an apparatus and methods for forming high quality buffer layers and Group III-V layers that are used to form a useful semiconductor device, such as a power device, light emitting diode (LED), laser diode (LD) or other useful device. Embodiments of the invention may also include an apparatus and methods for forming high quality buffer layers, Group III-V layers and electrode layers that are used to form a useful semiconductor device. In some embodiments, an apparatus and method includes the use of one or more cluster tools having one or more physical vapor deposition (PVD) chambers that are adapted to deposit a high quality aluminum nitride (AlN) buffer layer that has a high crystalline orientation on a surface of a plurality of substrates at the same time.

摘要翻译： 本文描述的本发明的实施例一般涉及用于形成高质量缓冲层的装置和方法，以及用于形成有用的半导体器件的III-V层，例如功率器件，发光二极管（LED），激光二极管 （LD）或其他有用的装置。 本发明的实施例还可以包括用于形成用于形成有用的半导体器件的高质量缓冲层，III-V族层和电极层的装置和方法。 在一些实施例中，装置和方法包括使用具有一个或多个物理气相沉积（PVD）室的一个或多个簇工具，其适于将具有高结晶取向的高质量氮化铝（AlN）缓冲层沉积在 同时是多个基板的表面。

公开(公告)号：US20150303071A1

公开(公告)日：2015-10-22

申请号：US14649114

申请日：2013-12-03

申请人： SILTRONIC AG ,  INTEL CORPORATION

发明人： Peter STORCK ,  Norbert WERNER ,  Martin VORDERWESTNER ,  Peter TOLCHINSKY ,  Irwin YABLOK

IPC分类号： H01L21/322 ,  H01L29/167 ,  H01L21/02

CPC分类号： H01L21/3225 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/3221 ,  H01L29/167

摘要： An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

摘要翻译： 外延晶片包括具有第一和第二侧的硅衬底晶片和沉积在第一侧上的硅外延层，以及可选地在硅外延层的顶部上的一个或多个另外的外延层，至少一个硅外延层或 所述一个或多个另外的外延层中的至少一个被掺杂浓度为1×1016原子/ cm3以上且1×1020原子/ cm3以下的氮。 通过在沉积气体气氛存在下通过化学气相沉积在940℃或更低的沉积温度下沉积硅外延层和/或一个或多个另外的外延层中的至少一个外延层来制造外延晶片， 一种或多种硅前体化合物和一种或多种氮前体化合物。

公开(公告)号：US20150294881A1

公开(公告)日：2015-10-15

申请号：US14250217

申请日：2014-04-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Hsiung Tsai ,  Clement Hsingjen Wann

IPC分类号： H01L21/324 ,  H01L21/268 ,  H01L21/322

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/2686 ,  H01L21/3221 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

摘要： The embodiments of processes and structures described above provide mechanisms for annealing defects by microwave anneal (MWA). MWA causes ionic/atomic (ionic and/or atomic) polarization, electronic polarization, and/or interfacial polarization in a substrate with dopants, damages, and interfaces in crystalline structures. The polarizations make the local temperatures higher than the substrate temperature. As a result, MWA can remove damages at a relatively low substrate temperature than other anneal mechanisms and is able to prevent undesirable dopant diffusion. The relatively low substrate temperature also makes MWA compatible with advanced processing technologies which demands lower substrate temperatures during front-end processing. MWA used in annealing defects (or damages) created in forming source and drain regions improves NMOS transistor performance.

摘要翻译： 上述方法和结构的实施方案提供了通过微波退火（MWA）退火缺陷的机制。 MWA在晶体结构中引起具有掺杂剂，损伤和界面的衬底中的离子/原子（离子和/或原子）极化，电子极化和/或界面极化。 极化使局部温度高于衬底温度。 因此，MWA可以在比其他退火机制低的基板温度下去除损坏，并且能够防止不需要的掺杂剂扩散。 相对较低的基板温度也使MWA与先进的处理技术相兼容，这在前端处理期间要求较低的基板温度。 用于在形成源极和漏极区域中产生的退火缺陷（或损伤）中的MWA改善了NMOS晶体管的性能。