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134 条记录 (耗时 0.028 秒)

    Printed wiring board
    122.
    发明授权
    Printed wiring board 有权
    印刷电路板

    公开(公告)号：US06740819B2

    公开(公告)日：2004-05-25

    申请号：US10421272

    申请日：2003-04-23

    申请人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

    发明人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

    IPC分类号： H05K706

    CPC分类号： H05K3/445 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4641 ,  H05K2203/143

    摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

    摘要翻译： 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。

    Method for producing printed circuit board with embedded decoupling capacitance
    123.
    发明授权
    Method for producing printed circuit board with embedded decoupling capacitance 有权
    具有嵌入式去耦电容的印刷电路板的制造方法

    公开(公告)号：US06739027B1

    公开(公告)日：2004-05-25

    申请号：US09553715

    申请日：2000-04-20

    申请人： John M. Lauffer ,  Konstantinos Papathomas

    发明人： John M. Lauffer ,  Konstantinos Papathomas

    IPC分类号： H01G700

    CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759 ,  Y10T29/43 ,  Y10T29/435

    摘要： A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

    摘要翻译： 提供了一种用于制造要嵌入电子电路封装的电容器的方法，包括以下步骤：选择第一导体箔，选择电介质材料，在第一导体箔的至少一侧上涂覆电介质材料， 在介质材料涂层的顶部具有第二导体箔的箔。 还要求保护的是包含至少一个根据本发明制造的嵌入式电容器的电子电路封装。

    Method for making a printed wiring board
    124.
    发明授权
    Method for making a printed wiring board 失效
    制造印刷线路板的方法

    公开(公告)号：US06608757B1

    公开(公告)日：2003-08-19

    申请号：US10101277

    申请日：2002-03-18

    申请人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

    发明人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

    IPC分类号： H05K716

    CPC分类号： H05K3/445 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4641 ,  H05K2203/143

    摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

    摘要翻译： 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。

    High performance dense wire for printed circuit board
    126.
    发明授权
    High performance dense wire for printed circuit board 有权
    高性能致密线用于印刷电路板

    公开(公告)号：US06495772B2

    公开(公告)日：2002-12-17

    申请号：US09834280

    申请日：2001-04-12

    申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

    发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

    IPC分类号： H05K102

    CPC分类号： H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0265 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  H01L2924/00

    摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

    摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

    Printed circuit board with wire adds and component adds having 7-shaped and semicircular terminations
    127.
    发明授权
    Printed circuit board with wire adds and component adds having 7-shaped and semicircular terminations 失效
    印刷电路板与电线添加和组件添加具有7形和半圆形终止

    公开(公告)号：US06369334B1

    公开(公告)日：2002-04-09

    申请号：US09404615

    申请日：1999-09-23

    申请人： John M. Lauffer

    发明人： John M. Lauffer

    IPC分类号： H05R909

    CPC分类号： H05K3/225 ,  H05K1/0292 ,  H05K1/112 ,  H05K3/0023 ,  H05K3/3452 ,  H05K3/4038 ,  H05K3/4652 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/09472 ,  H05K2203/0551

    摘要： An electronic circuit card and a process of manufacturing the electronic circuit card. The process includes the steps of providing the electronic circuit card with external electrical circuits. A photoimageable dielectric layer is formed on the electronic circuit card. A metal foil layer is laminated on the photoimageable dielectric layer and the metal foil layer is patterned to form a wire and a component add land pattern. The photoimageable dielectric layer is patterned and the wire and the component add land pattern are electrically connected to the electronic circuit card through a T-shaper or semicircular terminal.

    摘要翻译： 一种电子电路卡及其制造方法。 该过程包括为电子电路卡提供外部电路的步骤。 在电子电路卡上形成可光成像的电介质层。 在可光成像的介电层上层压金属箔层，对金属箔层进行图案化以形成导线和添加焊盘图案的部件。 可光成像介电层被图案化，并且线和元件添加焊盘图案通过T形成形器或半圆形端子电连接到电子电路卡。

    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby
    128.
    发明授权
    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby 有权
    在平面化薄膜电介质和由此制造的电路上设计和制造细线电路的方法

    公开(公告)号：US06290860B1

    公开(公告)日：2001-09-18

    申请号：US09283679

    申请日：1999-04-01

    申请人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    发明人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    IPC分类号： H01B1300

    CPC分类号： H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

    摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

    摘要翻译： 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

    Conductor interconnect with dendrites through film and method for producing same
    129.
    发明授权
    Conductor interconnect with dendrites through film and method for producing same 失效
    导体通过薄膜与树突互连，以及用于制造它的方法

    公开(公告)号：US06256874B1

    公开(公告)日：2001-07-10

    申请号：US09315305

    申请日：1999-05-20

    申请人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    发明人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

    IPC分类号： H05K336

    CPC分类号： H05K3/325 ,  H05K3/4614 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/10666 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49194

    摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”

    摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。