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    Process technology architecture of embedded DRAM
    121.
    发明授权
    Process technology architecture of embedded DRAM 有权
    嵌入式DRAM的工艺技术架构

    公开(公告)号：US06600186B1

    公开(公告)日：2003-07-29

    申请号：US09670328

    申请日：2000-09-27

    申请人： Jin-Yuan Lee ,  Mong-Song Liang

    发明人： Jin-Yuan Lee ,  Mong-Song Liang

    IPC分类号： H01L27108

    CPC分类号： H01L27/10897 ,  G11C11/4074 ,  G11C2207/104 ,  H01L21/823878

    摘要： Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

    摘要翻译： ASIC内的嵌入式DRAM单元具有带栅极氧化物的传输晶体管，其厚度等于逻辑核心的栅极氧化物的厚度。 这允许嵌入式DRAM单元由具有等于逻辑核心产生的电压电平的信号激活。 如果栅极氧化物的厚度等于外围电路的栅极氧化物厚度，则由字线电压发生器提供的信号的电压电平等于外围电路提供的电压，并且由位线电压发生器提供的信号具有 电压电平等于逻辑电路内的逻辑电路。 如果栅极氧化物的厚度等于逻辑电路的栅极氧化物的厚度，则由字线电压发生器提供的信号的电压电平等于由逻辑电路提供的电压，并且位线电压发生器具有 电压电平等于由逻辑电路提供的电压。

    Wafer burn-in design for DRAM and FeRAM devices
    122.
    发明授权
    Wafer burn-in design for DRAM and FeRAM devices 有权
    DRAM和FeRAM器件的晶片老化设计

    公开(公告)号：US06327682B1

    公开(公告)日：2001-12-04

    申请号：US09274001

    申请日：1999-03-22

    申请人： Pien Chien ,  Jin-Yuan Lee

    发明人： Pien Chien ,  Jin-Yuan Lee

    IPC分类号： G11C2900

    CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C11/401 ,  G11C29/006

    摘要： In this invention is disclosed a method of burn-in testing either DRAM's or FeRAM's at the wafer level. A stress voltage is applied across all storage capacitors of a DRAM or a FeRAM during a wafer level burn-in test to weed out memory chips with weak memory cells. Three pads are added to the memory chips to accommodate a burn-in signal, a word line voltage and a stress voltage. The burn-in signal disables normal memory operations, powers on all word lines, and connects a stress voltage across the storage capacitors of the memory cells. The stress voltage across the storage capacitors is the difference between the externally applied stress voltage and a low voltage from the bit lines that is connected to the memory cells by means of the word lines. The wafer level burn-in provides a way to improve throughput by eliminating weak product early in the manufacturing process.

    摘要翻译： 在本发明中公开了一种在晶片级别对DRAM或FeRAM进行老化测试的方法。 在晶片级老化测试期间，在DRAM或FeRAM的所有存储电容器上施加应力电压以除去具有弱存储器单元的存储器芯片。 三个焊盘被添加到存储器芯片以适应老化信号，字线电压和应力电压。 老化信号禁用正常的存储器操作，对所有字线通电，并连接存储器单元的存储电容器之间的应力电压。 存储电容器两端的应力电压是外部施加的应力电压与通过字线连接到存储单元的位线的低电压之间的差异。 晶圆级老化提供了一种通过在制造过程早期消除弱产品来提高吞吐量的方法。

    Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors
    123.
    发明授权
    Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors 失效
    用于具有沟槽状耦合电容器的电可编程只读存储器的非易失性存储单元

    公开(公告)号：US5801415A

    公开(公告)日：1998-09-01

    申请号：US947832

    申请日：1997-10-08

    申请人： Jin-Yuan Lee ,  Mong-Song Liang

    发明人： Jin-Yuan Lee ,  Mong-Song Liang

    IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76

    CPC分类号： H01L27/11521 ,  H01L29/42324

    摘要： A method for making an improved Electrically Programmable Read-Only-Memory (EPROM) device having non-volatile memory cells with enhanced capacitive coupling was achieved. The array of memory cells consists of a single field effect transistor (FET) having an additional floating gate. The FET is formed in a well etched into an insulating layer on the substrate surface. After forming the FET gate oxide, a polysilicon layer is patterned to form a trench-like floating gate with increased capacitive coupling. An interlevel dielectric layer is deposited. A second poly-silicon layer is deposited in the well and chem/mech polished back to form the control gate. The insulating layer having the wells is selectively removed. Lightly doped source/drain areas, self-aligned to the FET gate electrodes, are implanted and after forming sidewall spacers on the gate electrodes, source/drain contacts and buried bit lines are formed by a second implant. An insulating layer is deposited over the array of FETs having contact openings to the FET control gates. Another polysilicon layer is deposited and patterned to form the word lines. The word lines and buried bit lines are connected to the peripheral circuits to complete the EPROM chip.

    摘要翻译： 实现了具有增强的电容耦合的具有非易失性存储单元的改进的可编程只读存储器（EPROM）装置的方法。 存储器单元的阵列由具有附加浮置栅极的单个场效应晶体管（FET）组成。 FET被形成在衬底表面上被很好地刻蚀成绝缘层的阱中。 在形成FET栅极氧化物之后，将多晶硅层图案化以形成具有增加的电容耦合的沟槽状浮栅。 沉积层间电介质层。 第二个多晶硅层沉积在阱中，化学/机械表面抛光后形成控制栅极。 选择性地除去具有孔的绝缘层。 注入与FET栅电极自对准的轻掺杂源极/漏极区，并且在栅电极上形成侧壁间隔物之后，通过第二植入物形成源极/漏极接触和掩埋位线。 绝缘层沉积在具有与FET控制栅极的接触开口的FET阵列上。 沉积并图案化另一个多晶硅层以形成字线。 字线和掩埋位线连接到外围电路以完成EPROM芯片。

    Integrated circuit module fixing mechanism for temperature cycling test
    124.
    发明授权
    Integrated circuit module fixing mechanism for temperature cycling test 失效
    用于温度循环测试的集成电路模块固定机构

    公开(公告)号：US5752771A

    公开(公告)日：1998-05-19

    申请号：US761886

    申请日：1996-12-09

    申请人： King-Ho Ping ,  Jin-Yuan Lee

    发明人： King-Ho Ping ,  Jin-Yuan Lee

    IPC分类号： G01R1/04 ,  G01R31/28 ,  H01L21/673 ,  H05K13/00 ,  G01N17/00 ,  G01N3/60

    CPC分类号： G01R31/2867 ,  H05K13/0069 ,  G01R1/04

    摘要： An apparatus to retain integrated circuit modules during the preparation for a cycling of temperature, during the cycling of temperature, and during the post-handling after the cycling of temperature, is described. The apparatus has a specimen basket to contain the integrated circuit modules, a plurality of specimen retaining rods coupled to the specimen basket to prevent the integrated circuit modules from movement within the basket, a plurality of integrated circuit module retaining means coupled to the specimen retaining rods to secure each of the integrated circuit modules within the specimen basket, and a specimen securing rod retaining means to fasten each of the specimen retaining rods to the specimen basket.

    摘要翻译： 描述了在制备期间保持集成电路模块以在温度循环期间，在温度循环期间以及在温度循环之后的后处理期间保持集成电路模块的装置。 该装置具有容纳集成电路模块的标本篮，多个与样品篮结合的样本保持杆，以防止集成电路模块在篮内移动;多个集成电路模块保持装置，其连接到样本保持杆 将每个集成电路模块固定在试样篮内，以及试样固定杆保持装置，以将每个试样保持杆固定到试样篮上。

    Manufacture device of four transistor sram cell layout and device
    125.
    发明授权
    Manufacture device of four transistor sram cell layout and device 失效
    四晶体晶体管单元布局和器件的制造装置

    公开(公告)号：US5751044A

    公开(公告)日：1998-05-12

    申请号：US899737

    申请日：1997-07-24

    申请人： Jin-Yuan Lee

    发明人： Jin-Yuan Lee

    IPC分类号： G11C11/412 ,  H01L21/8244

    CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/904

    摘要： In accordance with still another aspect of this invention, a set of cross-coupled inverters provide a bistable flip flop formed on a semiconductor substrate with a pair of FOX regions defining an area on the surface of a substrate. The substrate is composed of a semiconductor material with a pair of buried contact regions in the silicon substrate juxtaposed with the FOX regions. A control gate electrode is formed on a gate oxide layer on the surface of the substrate between the pair of the FOX regions. A source region and drain region are formed in the substrate juxtaposed with the control gate electrode to form a parasitic FET device between the FOX regions, the source region and the drain region and reaching to separate ones of the buried contact regions. An interpolysilicon dielectric layer over the control gate electrode covers the device and the power supply conductor passes over the control gate electrode.

    摘要翻译： 根据本发明的另一方面，一组交叉耦合的反相器提供了形成在半导体衬底上的双稳态触发器，该双稳态触发器具有限定衬底表面上的区域的一对FOX区域。 衬底由半导体材料组成，硅衬底中与FOX区域并置的一对掩埋接触区域。 控制栅电极形成在一对FOX区域之间的衬底表面上的栅极氧化物层上。 源极区域和漏极区域形成在与控制栅电极并置的衬底中，以在FOX区域，源极区域和漏极区域之间形成寄生FET器件，并且到达分离的埋入接触区域。 控制栅电极上的多晶硅介电层覆盖器件，电源导体通过控制栅电极。

    Modified locus isolation process in which surface topology of the locos oxide is smoothed
    126.
    发明授权
    Modified locus isolation process in which surface topology of the locos oxide is smoothed 失效
    修改的轨迹分离过程，其中氧化物氧化物的表面拓扑平滑

    公开(公告)号：US5672538A

    公开(公告)日：1997-09-30

    申请号：US567015

    申请日：1995-12-04

    申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Sou-Wein Kuo

    发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Sou-Wein Kuo

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/31053 ,  H01L21/76202 ,  Y10S438/978

    摘要： A method for improving the surface topology silicon wafers during the fabrication of integrated circuits is described. Regions of silicon oxide isolation, incorporated into the silicon surface by thermal oxidation, frequently present an undesirable surface topology consisting of raised regions around their perimeter. These protrusions undermine the integrity of metallization lines subsequently deposited over them. Specifically, the metal lines tend to be thinner over the surface protrusions and consequently incur high failure rates. After the isolation regions are incorporated, a silicon oxide layer is deposited which is then etched back using a unidirectional anisotropic etching step which leaves behind portions of the layer in the regions of the steepest surface gradients. This results in smoothing out the irregularities and consequently provides for more uniform and reliable metallization lines.

    摘要翻译： 描述了在集成电路制造期间改进表面拓扑硅晶片的方法。 通过热氧化并入硅​​表面的氧化硅隔离区域经常呈现出不期望的表面拓扑结构，其周围包括凸起区域。 这些突起破坏随后沉积在其上的金属化线的完整性。 具体来说，金属线在表面突起上倾向于更薄，因此导致高故障率。 在并入隔离区之后，沉积氧化硅层，然后使用单向各向异性蚀刻步骤将其回蚀刻，该步骤在最陡的表面梯度的区域中留下该层的部分。 这导致平滑不规则性，并因此提供更均匀和可靠的金属化线。

    Method of eliminating buried contact trench in SRAM technology
    127.
    发明授权
    Method of eliminating buried contact trench in SRAM technology 失效
    在SRAM技术中消除埋接触沟的方法

    公开(公告)号：US5654231A

    公开(公告)日：1997-08-05

    申请号：US621273

    申请日：1996-03-25

    申请人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chun-Yi Shih

    发明人： Mong-Song Liang ,  Jin-Yuan Lee ,  Chun-Yi Shih

    IPC分类号： H01L21/28 ,  H01L21/8244

    CPC分类号： H01L27/11 ,  H01L21/28

    摘要： A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away where they are not covered by a buried contact mask to provide an opening to the semiconductor substrate. Ions are implanted through the opening into the semiconductor substrate to form a buried contact junction. A layer of dielectric material is deposited over the first polysilicon layer and over the semiconductor substrate within the opening. The layer is anisotropically etched to leave spacers on the sidewalls of the first polysilicon layer and adjacent the opening. A second layer of polysilicon is deposited overlying the first polysilicon layer and over the substrate within the opening. The second polysilicon layer is patterned to form gate electrodes and a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and a portion of a spacer overlying the buried contact junction is exposed and wherein a portion of the second polysilicon layer other than that of the contact remains as residue. The second polysilicon layer residue is etched away wherein the exposed spacer protects the buried contact junction within the semiconductor substrate from the etching to complete the formation of a buried contact in the fabrication of an integrated circuit.

    摘要翻译： 描述了形成改进的埋地接触结的新方法。 沉积在半导体衬底的表面上的栅极氧化硅层上的第一多晶硅层。 第一多晶硅和栅极氧化物层被蚀刻掉，其中它们不被掩埋的接触掩模覆盖以提供到半导体衬底的开口。 离子通过开口植入半导体衬底中以形成掩埋接触结。 电介质材料层沉积在开口内的第一多晶硅层上方和半导体衬底之上。 该层被各向异性地蚀刻以在第一多晶硅层的侧壁和邻近开口处留下间隔物。 第二层多晶硅沉积在第一多晶硅层的上方并且在开口内的衬底上。 图案化第二多晶硅层以形成栅电极和覆盖掩埋接触结的多晶硅接触，其中用于图案化的掩模不对准，并且覆盖掩埋接触结的间隔物的一部分被暴露，并且其中第二多晶硅层的一部分 除了接触物以外，残留物残留。 第二多晶硅层残留物被蚀刻掉，其中暴露的间隔物保护半导体衬底内的掩埋接触结点免受蚀刻，以在集成电路的制造中完成掩埋接触的形成。