公开(公告)号：US20020030978A1

公开(公告)日：2002-03-14

申请号：US09951341

申请日：2001-09-13

Inventor： Hiroki Kato

IPC: H05K007/06 ,  H05K007/02

CPC classification number: G02F1/13452 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/323 ,  H05K3/361 ,  H05K7/06 ,  H05K2201/09772 ,  H05K2201/10136 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2224/0401

Abstract: In a wiring board having a mounting region on which an integrated circuit having a plurality of terminals is mounted, and having a plurality of substrate-side wiring lines to be connected to the integrated circuit formed thereon, a conductor pattern is formed to extend in a substantially radial form from a prescribed, point in the mounting region to reach two or more of the substrate-side wiring lines to be grounded.

Abstract translation: 在具有安装有多个端子的集成电路的安装区域的布线板中，并且具有与形成在其上的集成电路连接的多个基板侧布线，形成导体图案以在 从安装区域中的规定点开始基本上径向地形成两个或更多个基板侧布线以接地。

公开(公告)号：US5847451A

公开(公告)日：1998-12-08

申请号：US721793

申请日：1996-09-25

Applicant: Toru Ohtaki ,  Yasuteru Ichida ,  Yasushi Takeuchi

Inventor： Toru Ohtaki ,  Yasuteru Ichida ,  Yasushi Takeuchi

IPC: H01L23/12 ,  H01L23/64 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K3/34 ,  H05K3/46 ,  H01L23/48 ,  H01L23/34 ,  H01L29/00 ,  H01L29/053

CPC classification number: H01L23/642 ,  H01L23/645 ,  H05K1/0233 ,  H05K1/165 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689 ,  H05K3/3421 ,  Y10S257/924

Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.

Abstract translation: 在其上安装有多个电源引脚和多个信号引脚的LSI的多层印刷电路板和采用该印刷电路板的栅格阵列封装中，多个电源引脚中的一些或全部 通过电感图案连接到电源图案，从而减少辐射噪声的产生。

公开(公告)号：US5683566A

公开(公告)日：1997-11-04

申请号：US649133

申请日：1996-05-14

Applicant: Ullrich Hetzler

Inventor： Ullrich Hetzler

IPC: H01C17/06 ,  H01C1/084 ,  H01C1/142 ,  H01C7/00 ,  H01C13/02 ,  H01C17/245 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01C1/142 ,  H01C1/084 ,  H01C13/02 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09281 ,  H05K2201/09772 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2203/162 ,  H05K2203/167 ,  Y02P70/611 ,  Y10T29/49099

Abstract: A resistor of SMD (Surface Mounted Device) construction includes a film of a resistive alloy as a resistive track on two electrically separated carrier plate elements of copper, which are constructed as contact elements solderable to the terminals of a printed circuit board to thereby ensure good heat dissipation into a printed circuit board. In order to manufacture such resistors, a resistive film sufficient for a plurality of individual resistors is adhered to but electrically isolated from a large copper plate and the laminate formed thereby is split into the individual resistors after producing the individual resistive tracks and their electrical connections to the copper plate and after producing gaps between the plate elements for each track.

Abstract translation: SMD（表面安装器件）结构的电阻器包括作为电阻轨道的两个电隔离的铜载体元件的电阻合金膜，其被构造为可焊接到印刷电路板的端子的接触元件，从而确保良好 散热成印刷电路板。 为了制造这种电阻器，可以将足够多个单独电阻器的电阻膜粘附到大铜板上而与之电隔离，并且由此形成的层叠体在产生各个电阻轨道及其与 并且在每个轨道的板元件之间产生间隙之后。

公开(公告)号：US5068631A

公开(公告)日：1991-11-26

申请号：US564998

申请日：1990-08-09

Applicant: Richard A. Vince

Inventor： Richard A. Vince

IPC: H05K1/14 ,  H03H1/00 ,  H05K1/02

CPC classification number: H05K1/0233 ,  H05K1/0225 ,  H05K1/0224 ,  H05K1/0231 ,  H05K2201/086 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689

Abstract: Electromagnetic filtering for a VLSI device having multiple power input leads is realized by employing a sub-power plane which is physically separate from a main power distribution system on a circuit board. The sub-power plane is placed directly under a corresponding VLSI device. Decoupling capacitors are connected to the sub-power plane and, in turn, to each of the power input leads on the VLSI device. Power is supplied from the main power distribution system to the sub-power plane via a ferrite bead type filter.

公开(公告)号：US5054060A

公开(公告)日：1991-10-01

申请号：US463792

申请日：1990-01-16

Applicant: David A. Werdin ,  Reinhold Henke

Inventor： David A. Werdin ,  Reinhold Henke

IPC: G06F13/40 ,  H05K1/02 ,  H05K7/14

CPC classification number: G06F13/409 ,  H05K1/0231 ,  H05K7/1445 ,  H05K2201/09772 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: A fiber optic to electrical conversion unit includes front and rear modular design with rear card modules conditioning signals to be passed to front modules. A frame synchronization method transmits a stream of multiplexing frames and periodically inserts a synchronization word in the stream. Prediction of the next synchronizing word in the receiving unit reduces the need to search for a synchronization word in the stream. Loop current regulation in a two-wire loop between a central office and a PBX uses a transformer serially connected in the two-wire circuit with a regulation circuit which holds the current in the loop within a predetermined range to permit the transformer to be held to a relatively small size. High frequency noise bypassing is accomplished by forming capacitor loops from the power connection to the ground connection of the component near to the component.

Abstract translation: 光纤到电气转换单元包括前后模块化设计，后置卡模块调理要传递到前模块的信号。 帧同步方法发送多路复用帧流，并在流中周期性地插入一个同步字。 接收单元中下一个同步字的预测减少了在流中搜索同步字的需要。 在中心局和集团电话之间的双线回路中的回路电流调节使用在双线电路中串联连接的变压器与调节电路，该调节电路将回路中的电流保持在预定范围内，以允许变压器保持 相对较小的尺寸。 通过从电源连接到组件附近的组件的接地连接形成电容器回路来实现高频噪声旁路。

公开(公告)号：US5027089A

公开(公告)日：1991-06-25

申请号：US247350

申请日：1988-09-21

Applicant: Reinhold Henke

Inventor： Reinhold Henke

IPC: G06F13/40 ,  H05K1/02 ,  H05K7/14

CPC classification number: H05K7/1445 ,  G06F13/409 ,  H05K1/0231 ,  H05K2201/09772 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: Apparatus and method for bypassing high frequency noise from a component mounted to a circuit board provides that the component be connected to the power and signal ground planes of the PC board with respective signal traces and that bypass capacitors be connected between these signal traces between the component and the signal and ground planes.

Abstract translation: 用于从安装到电路板的部件旁路高频噪声的装置和方法提供了组件通过相应的信号迹线连接到PC板的功率和信号接地层，并且旁路电容器连接在组件 和信号和地面。

公开(公告)号：US5012389A

公开(公告)日：1991-04-30

申请号：US284238

申请日：1988-12-14

Applicant: Richard A. Perry

Inventor： Richard A. Perry

IPC: G11C5/00 ,  H05K1/00 ,  H05K1/14 ,  H05K1/18

CPC classification number: H05K1/0296 ,  G11C5/00 ,  H05K1/181 ,  H05K1/141 ,  H05K1/18 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09772 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A high density memory module in which memory chips are mounted in an array of rows and columns on a printed circuit board. The circuit board includes groups of serpentine parallel conductors which extend along adjacent columns for connecting corresponding power, ground, control, address and data pins between the adjacent columns to one another. Adjacent groups of serpentine parallel conductors are nested within one another. According to the invention, high density packaging is provided for large chip arrays, using a minimum number to vias to interior board layers, and minimum interchip spacing.

Abstract translation: 一种高密度存储器模块，其中存储器芯片以印刷电路板上的行和列阵列的形式安装。 电路板包括一组蛇形平行导体，它们沿相邻的列延伸，用于将相邻列之间的相应电源，接地，控制，地址和数据引脚相互连接。 相邻的蛇形平行导体组彼此嵌套。 根据本发明，对于大型芯片阵列，使用最小数量的通向内部板层的通孔和最小的芯片间距来提供高密度封装。

公开(公告)号：US4891789A

公开(公告)日：1990-01-02

申请号：US163682

申请日：1988-03-03

Applicant: Victor L. Quattrini ,  Edwin P. Fisher

Inventor： Victor L. Quattrini ,  Edwin P. Fisher

IPC: G11C5/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: G11C5/00 ,  H05K1/112 ,  H05K1/181 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.

公开(公告)号：US4769525A

公开(公告)日：1988-09-06

申请号：US902376

申请日：1986-09-02

Applicant: James G. Leatham

Inventor： James G. Leatham

IPC: H05K3/34 ,  B23K1/00 ,  B23K1/018 ,  B29C65/34 ,  B29C65/76 ,  H01L23/40 ,  H05K1/02 ,  H05K3/30 ,  H05K3/32 ,  H05K7/20 ,  H05K13/04 ,  H05B3/36

CPC classification number: B29C66/472 ,  B23K1/018 ,  B29C65/3428 ,  B29C65/76 ,  H05K1/0212 ,  H05K13/0486 ,  H05K3/30 ,  H05K3/305 ,  B23K2201/42 ,  B29C65/348 ,  B29L2031/3425 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/0209 ,  H05K2201/09263 ,  H05K2201/09772 ,  H05K2201/10969 ,  H05K2203/1115 ,  H05K3/321 ,  H05K3/341 ,  H05K3/3494 ,  Y02P70/613

Abstract: A circuit package, or other device, (10) is mounted on a printed circuit board, or other substrate, (14) with an electrically conductive sinuous resistor wire structure 30 therebetween to define a space filled with adhesive. When the adhesive is set the package is held in place. When removal is desired, current is passed through the sinuous wire structure to soften the adhesive to permit removal of the package without damage to the package or the board.

Abstract translation: 电路封装或其他器件（10）安装在印刷电路板或其他衬底（14）上，其间具有导电的弯曲电阻器线结构30，以限定填充有粘合剂的空间。 当粘合剂被固定时，包装被保持就位。 当需要去除时，电流通过弯曲的线结构以软化粘合剂以允许去除包装而不损坏包装或板。

公开(公告)号：US4339785A

公开(公告)日：1982-07-13

申请号：US138438

申请日：1980-04-08

Applicant: Mitsuo Ohsawa

Inventor： Mitsuo Ohsawa

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34 ,  H05K7/02

CPC classification number: H05K1/0269 ,  H05K3/305 ,  H05K2201/09772 ,  H05K2201/10363 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2203/161 ,  H05K2203/168 ,  H05K3/3452 ,  H05K3/3468 ,  Y02P70/611 ,  Y02P70/613

Abstract: In an electronic circuit arrangement mounted on a printed circuit board in which leadless circuit parts are attached to the printed circuit board with adhesive. A white paint is applied onto a region to which adhesive is applied, and an adhesive containing pigment contrastable to the white paint is applied onto the paint.

Abstract translation: 在安装在印刷电路板上的电子电路装置中，其中无引线电路部分用粘合剂附接到印刷电路板。 将白色涂料施加到施加有粘合剂的区域上，并将与白色涂料对比的含有颜料的粘合剂施加到涂料上。