公开(公告)号：US6075700A

公开(公告)日：2000-06-13

申请号：US241351

申请日：1999-02-02

Applicant: Christopher Lee Houghton ,  Colin Edward Brench

Inventor： Christopher Lee Houghton ,  Colin Edward Brench

IPC: H01L23/367 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K1/18 ,  H05K7/20 ,  H05K9/00

CPC classification number: H05K9/0039 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/66 ,  H05K1/0218 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A method and apparatus are disclosed for attenuating RF noise produced by electronic systems by providing low RF impedance shorting of heat dissipating structures, such as heat sinks, to PCB reference planes. The RF impedance shorting path uses existing package pins with dedicated electrical paths through the package to the bottom surface of the heat sink. Such an arrangement provides very low RF impedance because of the minimal length and resistance of the shorting path, and also provides minimal disruption of the PCB design rules and tolerances by using existing package leads.

Abstract translation: 公开了一种方法和装置，用于通过向PCB参考平面提供诸如散热器之类的散热结构的低RF阻抗短路来衰减由电子系统产生的RF噪声。 RF阻抗短路路径使用现有的封装引脚，其具有穿过封装到散热器底表面的专用电路径。 这种布置提供非常低的RF阻抗，因为短路路径的最小长度和电阻，并且还通过使用现有封装引线来最小化PCB设计规则和公差的中断。

公开(公告)号：US6000126A

公开(公告)日：1999-12-14

申请号：US627909

申请日：1996-03-29

Applicant: Deepak Keshay Pai

Inventor： Deepak Keshay Pai

IPC: H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H01R9/00 ,  H01R43/00

CPC classification number: H05K3/303 ,  H01L23/49827 ,  H05K3/3426 ,  H01L2924/0002 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10946 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49222 ,  Y10T29/4981

Abstract: A method and apparatus is provided for connecting area grid array semiconductor chips to a printed wire board. A compliant lead matrix includes a carrier and a plurality of conductive leads arranged parallel to one another and secured relative to the carrier in the form of a matrix. The method includes orienting a first side of the lead matrix to be aligned with a reciprocal matrix of conductive surface pads on the area grid array semiconductor chip. First ends of the leads are electrically connected to the conductive surface pads of the area grid array chip. The second side of the lead matrix is oriented to be aligned with a reciprocal matrix of conductive surface pads on a printed wire board. Second ends of the leads of the lead matrix are electrically connected to the conductive surface pads of the printed wire board thereby establishing an electrical connection between the area grid array chip and the printed wire board.

Abstract translation: 提供了一种用于将区域阵列半导体芯片连接到印刷线路板的方法和装置。 柔性引线矩阵包括载体和彼此平行布置并以矩阵的形式相对于载体固定的多个导电引线。 该方法包括将引线矩阵的第一侧定向成与区域栅格阵列半导体芯片上的导电表面焊盘的倒数矩阵对准。 引线的第一端电连接到区域格栅阵列芯片的导电表面焊盘。 引线矩阵的第二面被定向成与印刷线路板上的导电表面焊盘的倒数矩阵对准。 引线矩阵的引线的第二端电连接到印刷线路板的导电表面焊盘，从而在区域格栅阵列芯片和印刷线路板之间建立电连接。

公开(公告)号：US5982635A

公开(公告)日：1999-11-09

申请号：US735832

申请日：1996-10-23

Applicant: L. William Menzies ,  Stephen W. Menzies ,  Dale S. Mackey

Inventor： L. William Menzies ,  Stephen W. Menzies ,  Dale S. Mackey

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/10 ,  H05K1/18

CPC classification number: H05K1/141 ,  H05K7/1092 ,  H05K1/0203 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10333 ,  H05K2201/10704 ,  H05K3/3447 ,  H05K3/368

Abstract: An interconnect structure adapts one or more signals conducted between a printed circuit board (PCB) and an integrated circuit (IC) including leads, the IC having signal requirements not provided by the PCB. The interconnect structure includes sockets that provideA. conductive paths between the circuit board and some, but not all, of the leads on the package. To adapt the signals, the interconnect structure also includes an intermediate adaptor board that includes one or more electrical components. The adaptor board and the sockets fit beneath the package containing the IC and above the PCB, and do not extend beyond the lateral boundaries of the package. Heat generated by these components during operation of the IC is dissipated through the IC package via a layer of thermally conductive material sandwiched between the component and the package. The intermediate adaptor board and the socket combine to perform all necessary signal conversion, including power supply voltage levels, between the circuit board and the IC.

Abstract translation: 互连结构适应在印刷电路板（PCB）和包括引线的集成电路（IC）之间传导的一个或多个信号，该IC具有不由PCB提供的信号要求。 互连结构包括提供A的插座。 导线之间的电路板和一些但不是全部的引线在封装上。 为了适应信号，互连结构还包括包括一个或多个电气部件的中间适配器板。 适配器板和插槽配置在包含IC和PCB上方的封装下方，并且不延伸超出封装的侧边界。 在IC运行期间由这些部件产生的热量通过夹在组件和封装之间的导热材料层通过IC封装消散。 中间适配器板和插座组合在电路板和IC之间执行所有必要的信号转换，包括电源电压电平。

公开(公告)号：US5870290A

公开(公告)日：1999-02-09

申请号：US909395

申请日：1997-08-11

Applicant: Collier S.C. Chun ,  Tom M. Skoric

Inventor： Collier S.C. Chun ,  Tom M. Skoric

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/10 ,  H01R23/68

CPC classification number: H05K1/141 ,  H05K7/1092 ,  H05K1/0262 ,  H05K2201/049 ,  H05K2201/0949 ,  H05K2201/10196 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K3/3436 ,  H05K3/368

Abstract: An interface adapter board according to the present invention can be inserted directly between two electronic parts without substantially displacing the electronic parts laterally. An electronic circuit board may include: (a) a first electronic part having a first array of conductors; (b) a second electronic part having a second array of conductors; and (c) an interface adapter board placed between the first and second electronic parts in such a way to minimize the lateral distance between each conductor of the first array and its respective conductor of the second array. The interface adapter board has a third array of conductors and a fourth array of conductors formed through the interface adapter board and positioned in an interstitial relationship with the third array of conductors. Each conductor of the first array is coupled to its respective conductor of the third array. A first set of conductors of the third array is directly coupled to its respective set of conductors of the fourth array. A second set of conductors of the third array is coupled to its respective set of conductors of the fourth array through an intermediate circuit so that the signals carried by the second set of conductors of the third array are different from the signals carried by its respective set of conductors of the fourth array. Each conductor of the fourth array is coupled to its respective conductor of the second array.

Abstract translation: 根据本发明的接口适配器板可以直接插入两个电子部件之间，而不会使电子部件基本上位移。 电子电路板可以包括：（a）具有第一阵列导体的第一电子部件; （b）具有第二阵列阵列的第二电子部件; 以及（c）以使得第一阵列的每个导体与其第二阵列的相应导体之间的横向距离最小化的方式设置在第一和第二电子部件之间的接口适配器板。 接口适配器板具有第三导体阵列和第四导体阵列，其通过接口适配器板形成，并且与第三阵列导体定位成间隙关系。 第一阵列的每个导体耦合到其相应的第三阵列的导体。 第三阵列的第一组导体直接耦合到其第四阵列的相应导体组。 第三阵列的第二组导体通过中间电路耦合到其第四阵列的相应导体组，使得由第三阵列的第二组导体承载的信号与由其相应组所携带的信号不同 的第四阵列的导体。 第四阵列的每个导体耦合到其相应的第二阵列的导体。

公开(公告)号：US5682297A

公开(公告)日：1997-10-28

申请号：US615155

申请日：1996-03-12

Applicant: David J. Silva

Inventor： David J. Silva

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K1/0206 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09954 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10704 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A dual footprint for servicing either of two types of microprocessor packaging systems. A first footprint capable of receiving and servicing a first type of microprocessor packaging system, for example, a tape carrier package microprocessor package, is formed within a second footprint capable of receiving and servicing a second type of microprocessor packaging system, for example, a pin grid array microprocessor package. In a preferred form, the two footprints are electrically interconnected and the first footprint is offset by a selected angle from the second footprint to allow increased connectivity between the two footprints.

Abstract translation: 用于维护两种微处理器封装系统中的任一种的双重封装。 能够接收和维护第一类型的微处理器封装系统（例如，载带封装微处理器封装）的第一覆盖区形成在能够接收和维护第二类微处理器封装系统的第二覆盖区内，例如，引脚 网格阵列微处理器封装。 在优选形式中，两个覆盖区是电互连的，并且第一覆盖区从第二覆盖区偏移选定的角度以允许两个覆盖区之间的连接增加。

公开(公告)号：US5557505A

公开(公告)日：1996-09-17

申请号：US278798

申请日：1994-07-22

Applicant: David J. Silva

Inventor： David J. Silva

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K1/0206 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09954 ,  H05K2201/10681 ,  H05K2201/10689 ,  H05K2201/10704 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A dual footprint for servicing either of two types of microprocessor packaging systems. A first footprint capable of receiving and servicing a first type of microprocessor packaging system, for example, a tape carrier package microprocessor package, is formed within a second footprint capable of receiving and servicing a second type of microprocessor packaging system, for example, a pin grid array microprocessor package. In a preferred form, the two footprints are electrically interconnected and the first footprint is offset by a selected angle from the second footprint to allow increased connectivity between the two footprints.

Abstract translation: 用于维护两种微处理器封装系统中的任一种的双重封装。 能够接收和维护第一类型的微处理器封装系统（例如，载带封装微处理器封装）的第一覆盖区形成在能够接收和维护第二类微处理器封装系统的第二覆盖区内，例如，引脚 网格阵列微处理器封装。 在优选形式中，两个覆盖区是电互连的，并且第一覆盖区从第二覆盖区偏移选定的角度以允许两个覆盖区之间的连接增加。

公开(公告)号：US5481436A

公开(公告)日：1996-01-02

申请号：US330746

申请日：1994-10-18

Applicant: William E. Werther

Inventor： William E. Werther

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/10 ,  H05K1/11

CPC classification number: H05K1/141 ,  H05K3/3415 ,  H05K7/1084 ,  H05K7/1092 ,  H01L2924/15312 ,  H05K1/0262 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/368 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49139

Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed. The interconnect board can have layers assigned to specific voltages, in a power-translation design.

Abstract translation: 公开了用于互连集成电路，特别是预先包装的集成电路的组件和方法。 由引脚载体，一组焊盘（例如用于接收表面安装的集成电路）和耦合焊盘和引脚的一组导电路径组成的多电平电气组件可以将一个或多个集成电路连接到 插座或电路板的其他连接区域。 路径通过多层互连板，其可以被配置为允许将焊盘任意平移到引脚用于不同目的，或者允许附加电路元件（例如协处理器或无源电路）与路径的耦合。 还公开了用于形成组件的本发明的方法以及组件的实施例可用于增加电路板密度的本发明的系统。 在电源转换设计中，互连板可以分配给特定电压的层。

公开(公告)号：US5460531A

公开(公告)日：1995-10-24

申请号：US187927

申请日：1994-01-27

Applicant: Joseph A. Vivio

Inventor： Joseph A. Vivio

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/36 ,  H05K7/10 ,  H01L23/52

CPC classification number: H05K7/1084 ,  H05K1/141 ,  H05K7/1092 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10333 ,  H05K2201/10704 ,  H05K3/368

Abstract: An interconnect structure is provided for converting or adapting select signals sent between a printed circuit board (PCB) and an electrical component. The interconnect structure comprises an adapter card placed between the PCB and the electrical component, wherein the adapter card includes one or more pass-through vias and non pass-through vias extending completely through the adapter card in parallel spaced relation to one another. Pass-through vias are used to couple signals having critical timing paths between the electrical component and the PCB without substantially modifying or changing the critical path switch points. The pass-through vias also provide connection of signals of non critical timing between the PCB and the component. A signal converter may be used to convert non-critical signals and place those signals at select pins upon the electrical component. Thus, the adapter card is well suited for providing conversion to newer, updated components which are pin-for-pin compatible with, and which operate at dissimilar voltages from, older components. The adapter card performs all necessary signal conversion without requiring modification to the larger PCB.

Abstract translation: 提供互连结构，用于转换或调整在印刷电路板（PCB）和电气部件之间发送的选择信号。 互连结构包括放置在PCB和电气部件之间的适配器卡，其中适配器卡包括一个或多个穿过通孔和非穿过通孔，其彼此平行地间隔开地完全延伸穿过适配器卡。 穿通通孔用于将具有关键定时路径的信号耦合在电气部件和PCB之间，而不必基本上修改或改变关键路径切换点。 直通通孔还提供PCB和组件之间非关键定时信号的连接。 信号转换器可用于转换非关键信号，并将这些信号放置在电气部件上的选定引脚处。 因此，适配器卡非常适合于提供与更旧的更新的组件的转换，这些更新的组件是针对引脚兼容的，并且在旧组件中以不同的电压工作。 适配器卡执行所有必要的信号转换，无需修改较大的PCB。

公开(公告)号：US5337219A

公开(公告)日：1994-08-09

申请号：US719425

申请日：1991-06-24

Applicant: Dennis C. Carr ,  Edward P. McLeskey ,  Frank H. Sarnacki

Inventor： Dennis C. Carr ,  Edward P. McLeskey ,  Frank H. Sarnacki

IPC: H01L23/538 ,  H05K3/00 ,  H05K3/22 ,  H05K3/42 ,  H05K1/11

CPC classification number: H01L23/5385 ,  H05K3/225 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/19107 ,  H05K2201/09572 ,  H05K2201/10287 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/175 ,  H05K3/0047 ,  H05K3/42

Abstract: A method for altering an electrical connection in an electronic package including one or more semiconductor chips overlying, i.e., mounted directly onto, or mounted onto one or more modules which are mounted onto, a substrate such as a printed circuit card or printed circuit board, as well as the resulting electronic package, is disclosed. In accordance with a preferred embodiment of the inventive method, at least one plated, solder-filled hole in the substrate is drilled out to eliminate an unwanted electrical connection. A solder region, e.g., a solder ball, is inserted into the drilled out hole into contact with an electrically conductive member, e.g., an electrically conductive pin, extending from, for example, a module into the hole. A cylinder, including a central core of electrically conductive material, encircled by an annulus of electrically insulating material, is inserted into the hole. The solder region is then reflowed to form an electrical and metallurgical bond between the module member and the central core. A new electrical connection is completed by extending a wire bond from the bottom of the central core to the bottom of the central core in another such hole or to the bottom of a solder-filled hole.

Abstract translation: 一种用于改变包括一个或多个半导体芯片的电子连接的方法，所述半导体芯片重叠，即直接安装在或安装在安装到诸如印刷电路板或印刷电路板的基板上的一个或多个模块上， 以及所得到的电子封装。 根据本发明方法的优选实施例，钻出衬底中的至少一个电镀的焊料填充孔以消除不期望的电连接。 焊料区域例如焊球被插入到钻孔中，与例如导电销（例如，模块）延伸到孔中的导电构件接触。 包括导电材料的中心芯的圆筒，被电绝缘材料的环形区域包围，插入孔中。 焊料区域然后回流以在模块构件和中心芯之间形成电和冶金结合。 通过将引线接合从中心芯的底部延伸到另一个这样的孔中的中心芯的底部或焊料填充的孔的底部来完成新的电连接。

公开(公告)号：US5257165A

公开(公告)日：1993-10-26

申请号：US834841

申请日：1992-02-13

Applicant: Jung-Shan Chiang

Inventor： Jung-Shan Chiang

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36 ,  H05K1/00

CPC classification number: H05K1/141 ,  H05K1/18 ,  H05K2201/049 ,  H05K2201/10303 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K3/3447 ,  H05K3/368

Abstract: A PGA adaptor mounting hardware comprising a PGA adaptor which has a plurality of double-head fastening pins and contact pins with flush type contact terminals, and a printed circuit board which has apertures, a printed circuit with conductive points on a top edge thereof, and a transistor circuit on a bottom edge thereof with contact terminals aligned to and electrically connected to the conductive points of the printed circuit for mounting an IC. The printed circuit board is covered with a layer of tin paste over the apertures and the contact terminals of the printed circuit thereby, permitting the PGA adaptor to be connected thereto by inserting the double-head fastening pins into the apertures and, soldering the contact terminals of the contact pins to the conductive points of the printed circuit.

Abstract translation: 一种PGA适配器安装硬件，包括具有多个双头紧固销和具有齐平型接触端子的接触针的PGA适配器，以及具有孔的印刷电路板，在其顶部边缘上具有导电点的印刷电路，以及 在其底部边缘上的晶体管电路，其接触端子对准并电连接到用于安装IC的印刷电路的导电点。 印刷电路板被覆盖在印刷电路的孔和接触端子上，从而允许PGA适配器通过将双头紧固销插入孔而连接到其上，并焊接接触端子 的接触针到印刷电路的导电点。