公开(公告)号：US20160098223A1

公开(公告)日：2016-04-07

申请号：US14967934

申请日：2015-12-14

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Abstract translation: 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。

公开(公告)号：US09201705B2

公开(公告)日：2015-12-01

申请号：US14247783

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F9/50 ,  G06F12/02 ,  G06F3/06 ,  G06F13/38 ,  G11C14/00 ,  G11C13/00

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。

公开(公告)号：US20150286585A1

公开(公告)日：2015-10-08

申请号：US14677712

申请日：2015-04-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F12/14

CPC classification number: G06F12/1458 ,  G06F12/1408 ,  G06F21/79 ,  G06F2212/1052

Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.

Abstract translation: 设备包括存储器。 该设备还包括一个控制器。 所述控制器包括：寄存器，被配置为存储所接收的命令是否能够改变所述存储器的访问保护方案的能力的指示。 接收到的命令可以响应于该指示而改变对存储器的访问保护方案的访问。

公开(公告)号：US20140351675A1

公开(公告)日：2014-11-27

申请号：US14456559

申请日：2014-08-11

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G06F11/10 ,  G06F1/32 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。

公开(公告)号：US20250156272A1

公开(公告)日：2025-05-15

申请号：US19021490

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US20250077348A1

公开(公告)日：2025-03-06

申请号：US18776730

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Antonino Capri' ,  Daniele Balluchi ,  Joseph M. McCrate ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F11/10

Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US12230311B2

公开(公告)日：2025-02-18

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Cagdas Dirik ,  Robert M. Walker ,  Sujeet Ayyapureddi ,  Niccolo Izzo ,  Markus Geiger ,  Yang Lu ,  Ameen Akel ,  Elliott C. Cooper-Balis ,  Danilo Caraccio

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US12197631B2

公开(公告)日：2025-01-14

申请号：US17562916

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/10 ,  G06F21/55 ,  G06F21/60 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US12099457B2

公开(公告)日：2024-09-24

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

CPC classification number: G06F13/1694

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

公开(公告)号：US20240096439A1

公开(公告)日：2024-03-21

申请号：US18169635

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Greg S. Hendrix ,  Anandhavel Nagendrakumar ,  Krunal Patel ,  Kirthi Shenoy ,  Danilo Caraccio ,  Ankush Lal ,  Frank F. Ross ,  Adam D. Gailey

IPC: G11C29/00 ,  G11C29/52

CPC classification number: G11C29/76 ,  G11C29/52

Abstract: In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.