公开(公告)号：US09741829B2

公开(公告)日：2017-08-22

申请号：US14714227

申请日：2015-05-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US09735274B2

公开(公告)日：2017-08-15

申请号：US14947650

申请日：2015-11-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/76877 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/78696

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

公开(公告)号：US09735257B2

公开(公告)日：2017-08-15

申请号：US14884277

申请日：2015-10-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/6681 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

公开(公告)号：US20170229456A1

公开(公告)日：2017-08-10

申请号：US15496507

申请日：2017-04-25

申请人： Samsung Electronics Co., Ltd.

发明人： Deepak SHARMA ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC分类号： H01L27/0886 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681

摘要： Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US09716177B2

公开(公告)日：2017-07-25

申请号：US14983217

申请日：2015-12-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Bartlomiej Jan Pawlak ,  Behtash Behin-Aein ,  Mehdi Salmani-Jelodar

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/6681

摘要： The device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure including first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure includes the first, second and third layers of semiconductor material.

公开(公告)号：US20170194356A1

公开(公告)日：2017-07-06

申请号：US14984118

申请日：2015-12-30

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Chi-Chun Liu

IPC分类号： H01L27/12 ,  H01L23/58 ,  H01L21/308 ,  H01L21/84 ,  H01L27/02

CPC分类号： H01L27/1211 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/845 ,  H01L23/58 ,  H01L27/0207 ,  H01L29/6681

摘要： Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.

公开(公告)号：US09691818B2

公开(公告)日：2017-06-27

申请号：US14839335

申请日：2015-08-28

申请人： SK hynix Inc.

发明人： Suk Ki Kim

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L29/66 ,  H01L27/22 ,  H01L27/10 ,  H01L21/762 ,  H01L29/786 ,  H01L29/49 ,  H01L29/165 ,  H01L29/267

CPC分类号： H01L27/2436 ,  H01L21/7624 ,  H01L27/101 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/165 ,  H01L29/267 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6681 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/141 ,  H01L45/147 ,  H01L45/16

摘要： A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material.

公开(公告)号：US09691758B1

公开(公告)日：2017-06-27

申请号：US15068068

申请日：2016-03-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Hsin Hu ,  Hsueh-Shih Fan ,  Huan-Tsung Huang

IPC分类号： H01L21/8234 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/16 ,  H01L29/24 ,  H01L29/267 ,  H01L21/205

CPC分类号： H01L27/0629 ,  H01L21/2053 ,  H01L21/76895 ,  H01L21/823431 ,  H01L23/535 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66166 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.

公开(公告)号：US20170179251A1

公开(公告)日：2017-06-22

申请号：US15293572

申请日：2016-10-14

申请人： International Business Machines Corporation

发明人： KARTHIK BALAKRISHNAN ,  POUYA HASHEMI ,  SANGHOON LEE

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L21/845 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3081 ,  H01L21/31056 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78696

摘要： A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a orientation wherein the hard mask is oriented in the direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

公开(公告)号：US09685555B2

公开(公告)日：2017-06-20

申请号：US14584161

申请日：2014-12-29

申请人： STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Qing Liu ,  Nicolas Loubet ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

CPC分类号： H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

摘要： Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.