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    Permutational memory cells
    133.
    发明授权
    Permutational memory cells 有权
    占位记忆细胞

    公开(公告)号：US09484088B2

    公开(公告)日：2016-11-01

    申请号：US14665794

    申请日：2015-03-23

    申请人： Micron Technology, Inc.

    发明人： Scott E. Sills

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C13/00 ,  G11C11/00 ,  G11C11/50 ,  G11C7/18 ,  G11C8/00 ,  G11C11/56 ,  G11C8/14 ,  G11C19/00

    CPC分类号： G11C13/0011 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/00 ,  G11C11/50 ,  G11C11/56 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0069 ,  G11C19/00 ,  G11C2213/52

    摘要： Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the at least one RCM cell. A first portion of the pairs are arranged laterally to one another in a first grouping and a second opposing portion of the pairs are arranged laterally to one another in a second grouping. A memory cell material is disposed between opposing sides of the pairs of the three or more electrical contacts. The memory cell material is configured to form a conductive pathway between one or more of the pairs, with each of the three or more pairs being configured to be accessed individually for at least one operation including program, erase, and read operations. Additional apparatuses and methods are described.

    摘要翻译： 各种实施例包括至少一个电阻变化存储器（RCM）单元。在一个实施例中，三个或更多对电触点耦合到至少一个RCM单元。 成对的第一部分在第一组中彼此横向地布置，并且对的第二相对部分在第二组中彼此横向地布置。 存储单元材料设置在三个或更多个电触点对的相对侧之间。 存储单元材料被配置为在一对或多对之间形成导电路径，其中三对或更多对中的每一对被配置为分别访问包括程序，擦除和读取操作的至少一个操作。 描述附加的装置和方法。

    Memory circuit having shared word line
    135.
    发明授权
    Memory circuit having shared word line 有权
    具有共享字线的存储电路

    公开(公告)号：US09449667B2

    公开(公告)日：2016-09-20

    申请号：US14459094

    申请日：2014-08-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro Fujiwara ,  Li-Wen Wang ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC分类号： G11C8/14 ,  G11C11/418 ,  H01L27/02 ,  H01L27/11

    CPC分类号： G11C11/419 ,  G11C8/14 ,  G11C11/418 ,  H01L27/0207 ,  H01L27/1116

    摘要： A memory circuit includes a plurality of memory cells arranged into columns and one or more pairs of adjacent rows and one or more first word lines. Each memory cell of the plurality of memory cells includes a data node, a first access node, and a first pass gate coupled to the first access node and configured to selectively alter a voltage level at the first access node according to a voltage level at the data node if the first pass gate is turned on. A word line of the one or more first word lines is coupled with the first pass gates of a pair of the one or more pairs of adjacent rows, and the first pass gates of the pair of the one or more pairs of adjacent rows are configured to be selectively turned on responsive to a voltage level at the word line.

    摘要翻译： 存储电路包括布置成列和一对或多对相邻行和一个或多个第一字线的多个存储单元。 多个存储单元的每个存储器单元包括数据节点，第一接入节点和耦合到第一接入节点的第一通过门，并且被配置为根据第一接入节点的电压电平有选择地改变第一接入节点处的电压电平 数据节点，如果第一个传递门被打开。 所述一个或多个第一字线的字线与所述一对或多对相邻行的第一传递门耦合，并且所述一对或多对相邻行中的所述一对的第一传递门被配置 根据字线上的电压电平有选择地接通。

    Memory device with different memory film diameters in the same laminate level
    136.
    发明授权
    Memory device with different memory film diameters in the same laminate level 有权
    具有不同记忆膜直径的存储器件处于相同层压板级

    公开(公告)号：US09425207B2

    公开(公告)日：2016-08-23

    申请号：US14521577

    申请日：2014-10-23

    申请人： Kabushiki Kaisha Toshiba

    发明人： Naoki Yasuda

    IPC分类号： H01L27/115 ,  G11C16/14 ,  G11C11/56 ,  G11C8/14 ,  G11C16/04 ,  G11C29/50

    CPC分类号： H01L27/11582 ,  G11C8/14 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/14 ,  G11C29/50016 ,  H01L27/11565

    摘要： According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film.

    摘要翻译： 根据一个实施例，非易失性存储器件包括第一电极，至少一个第一半导体层，第一存储膜，第二电极，至少一个第二半导体层和第二存储膜。 第一电极沿第一方向堆叠。 一个第一半导体层沿第一方向延伸穿过第一电极。 第一记忆膜设置在每个第一电极和一个第一半导体层之间。 第二电极在第一方向上堆叠并且在与第一方向正交的第二方向上与第一电极一起设置。 第一半导体层沿第一方向延伸穿过第二电极。 第二记忆膜设置在每个第二电极和一个第二半导体层之间。 第一存储膜的外径大于第二存储膜的外径。

    Dual-port static random-access memory cell
    137.
    发明授权
    Dual-port static random-access memory cell 有权
    双端口静态随机存取存储单元

    公开(公告)号：US09418728B2

    公开(公告)日：2016-08-16

    申请号：US14339883

    申请日：2014-07-24

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon Jhy Liaw

    IPC分类号： G11C11/412 ,  H01L27/11 ,  H01L29/78 ,  G11C5/06 ,  G11C8/14 ,  G11C8/16

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/785

    摘要： The present disclosure provides a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down (PD) device, and a second PD device; a second inverter cross-coupled to the first inverter, the second inverter including a second PU device, a third PD device, and a fourth PD device; first and second pass gate (PG) devices coupled to the first inverter to form a first port; and third and fourth PG devices coupled to the second inverter to form a second port. The first and second PG devices, the first PD device of the first inverter, and the third PD device of the second inverter are configured on a first active region. The third and fourth PG devices, the second PD device of the first inverter, and the fourth PD device of the second inverter are configured on a second active region.

    摘要翻译： 本公开提供了一种包括第一反相器的静态随机存取存储器（SRAM）单元，所述第一反相器包括第一上拉（PU）器件，第一下拉（PD）器件和第二PD器件; 与第一反相器交叉耦合的第二反相器，第二反相器包括第二PU器件，第三PD器件和第四PD器件; 耦合到所述第一反相器的第一和第二传递门（PG）器件以形成第一端口; 以及耦合到所述第二反相器的第三和第四PG器件，以形成第二端口。 第一和第二PG器件，第一反相器的第一PD器件和第二反相器的第三PD器件被配置在第一有源区域上。 第三和第四PG器件，第一反相器的第二PD器件和第二反相器的第四PD器件被配置在第二有源区域上。

    Memory apparatus and system with shared wordline decoder
    138.
    发明授权
    Memory apparatus and system with shared wordline decoder 有权
    具有共享字线解码器的存储器和系统

    公开(公告)号：US09406363B2

    公开(公告)日：2016-08-02

    申请号：US14261674

    申请日：2014-04-25

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

    IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C5/02 ,  G11C8/14

    CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C8/14

    摘要： A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

    摘要翻译： 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

    Apparatuses and methods for providing word line voltages during standby
    140.
    发明授权
    Apparatuses and methods for providing word line voltages during standby 有权
    在待机期间提供字线电压的装置和方法

    公开(公告)号：US09299406B2

    公开(公告)日：2016-03-29

    申请号：US13399785

    申请日：2012-02-17

    申请人： Harish N. Venkata

    发明人： Harish N. Venkata

    IPC分类号： G11C7/20 ,  G11C7/00 ,  G11C8/08 ,  G11C8/14

    CPC分类号： G11C7/20 ,  G11C7/00 ,  G11C8/08 ,  G11C8/14

    摘要： Apparatuses and methods of providing word line voltages include an example apparatus including a voltage driver and a word line driver. The voltage driver is configured to provide a word line voltage, wherein the word line voltage is a pumped supply voltage responsive to an active mode and the word line voltage is a non-zero voltage less than the pumped supply voltage during a standby mode. The word line driver is coupled to the voltage driver and is configured to drive a respective word line to the word line voltage during the active and standby modes.

    摘要翻译： 提供字线电压的装置和方法包括包括电压驱动器和字线驱动器的示例性装置。 电压驱动器被配置为提供字线电压，其中字线电压是响应于活动模式的泵浦电源电压，并且字线电压是在待机模式期间小于泵浦电源电压的非零电压。 字线驱动器耦合到电压驱动器，并且被配置为在主动和待机模式期间将相应字线驱动到字线电压。