公开(公告)号：US20110248328A1

公开(公告)日：2011-10-13

申请号：US12757172

申请日：2010-04-09

申请人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底上的第一浮置栅极，浮置栅极具有凹面侧面; 第一个浮动门上的第一个控制门; 与所述第一控制栅极相邻的第一间隔件; 与所述第一浮动栅极的第一侧相邻的第一字线，具有第一距离; 以及与所述第一浮动栅极的第二侧相邻的擦除栅极，其具有小于所述第一距离的第二距离，所述第二侧与所述第一侧相对。

公开(公告)号：US07883917B2

公开(公告)日：2011-02-08

申请号：US12354171

申请日：2009-01-15

申请人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4807 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48505 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/45124 ,  H01L2224/05655 ,  H01L2924/00

摘要： A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.

摘要翻译： 公开了一种用焊盘形成半导体器件的方法。 提供具有器件面积和接合面积的第一衬底，其中第一衬底具有上表面和底表面。 半导体元件形成在器件区域中的第一衬底的上表面上。 在接合区域中的基板的上表面上形成第一金属间介电层。 在第一金属间介质层中形成最下面的金属图案，其中最下面的金属图形用作接合焊盘。 形成通过第一基板的开口以露出最下面的金属图案。

公开(公告)号：US07824998B2

公开(公告)日：2010-11-02

申请号：US12357661

申请日：2009-01-22

申请人： Yuan-Hung Liu ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/20

CPC分类号： H01L21/02274 ,  H01L21/02115 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/14632 ,  H01L27/14687 ,  H01L28/91 ,  H01L29/42328 ,  H01L29/7881

摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.

摘要翻译： 一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。 在第二电介质层上并在开口内形成基本上共形的含金属层。 去除第二电介质层和一部分含金属层。 通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。 在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

公开(公告)号：US20100244287A1

公开(公告)日：2010-09-30

申请号：US12415005

申请日：2009-03-31

申请人： Alex Hsu ,  Shih-Chi Fu ,  Feng-Jia Shiu ,  Chia-Shiung Tsai

发明人： Alex Hsu ,  Shih-Chi Fu ,  Feng-Jia Shiu ,  Chia-Shiung Tsai

IPC分类号： H01L23/544 ,  H01L21/30

CPC分类号： G03F9/7084 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/7088

摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有前侧和后侧的器件衬底，器件衬底具有第一折射率，在器件衬底的前侧上形成嵌入的靶，在嵌入的靶上形成反射层，形成介质 所述介质层具有小于所述第一折射率的第二折射率，并且从所述背面将辐射从所述介质层和所述器件基板突出以使得所述嵌入的靶被检测为半导体 处理。

公开(公告)号：US07785966B2

公开(公告)日：2010-08-31

申请号：US11614677

申请日：2006-12-21

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

摘要翻译： 一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。 该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

公开(公告)号：US20100193891A1

公开(公告)日：2010-08-05

申请号：US12756743

申请日：2010-04-08

申请人： Yung-Hung Wang ,  Yu-Jen Wang ,  Mark Juang ,  Chia-Shiung Tsai

发明人： Yung-Hung Wang ,  Yu-Jen Wang ,  Mark Juang ,  Chia-Shiung Tsai

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  H01L43/08 ,  H01L43/12

摘要： A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.

摘要翻译： 形成集成电路的方法包括形成磁隧道结（MTJ）层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层，其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。

公开(公告)号：US07732299B2

公开(公告)日：2010-06-08

申请号：US11673652

申请日：2007-02-12

申请人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiang Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Cheng ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

发明人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiang Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Cheng ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

IPC分类号： H01L21/338 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L23/585 ,  B81C1/0038 ,  B81C1/00611 ,  B81C2201/0125 ,  H01L21/31053 ,  H01L21/31056 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

摘要翻译： 本公开提供了一种制造微电子器件的方法。 该方法包括在第一衬底上形成顶部金属层，其中顶部金属层具有多个互连特征和第一虚拟特征; 在顶部金属层上形成第一介电层; 在与多个互连特征和顶部金属层的第一虚拟特征基本上垂直对准的目标区域中蚀刻第一介电层; 在第一介电层上进行化学机械抛光（CMP）工艺; 然后将第一基板接合到第二基板。

公开(公告)号：US07700473B2

公开(公告)日：2010-04-20

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧上的尺寸上横向减小以产生底切。

公开(公告)号：US07692230B2

公开(公告)日：2010-04-06

申请号：US11674581

申请日：2007-02-13

申请人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

发明人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

IPC分类号： H01L27/108

CPC分类号： H01L43/12 ,  B82Y10/00 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08

摘要： Disclosed herein is an improved memory device wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

摘要翻译： 这里公开了一种改进的存储装置，其中由常规着陆垫占据的面积显着地减小到常规着陆垫占据的面积的大约50％至10％。 这是通过从电池结构中移除着陆焊盘而实现的，而是形成导电通孔结构，其提供从结构中的存储器堆或器件到下金属层的电连接。 通过仅形成该通孔结构，而不是形成在着陆焊盘的任一侧上的分离的通孔，结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小，因此通孔结构和下面 金属层可以形成为更靠近存储器堆叠（或与堆叠相关联的导体），以便减小电池结构的整体宽度。

公开(公告)号：US07687794B2

公开(公告)日：2010-03-30

申请号：US11781728

申请日：2007-07-23

申请人： Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/02

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

摘要翻译： PCRAM（相变随机存取存储器）半导体器件中的PCM（相变存储器）单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后，使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。