公开(公告)号：US20070277997A1

公开(公告)日：2007-12-06

申请号：US11421481

申请日：2006-06-01

Applicant: Wei-An Liang ,  Chung-Ju Wu ,  Yin-Chieh Hsueh

Inventor： Wei-An Liang ,  Chung-Ju Wu ,  Yin-Chieh Hsueh

IPC: H05K1/03

CPC classification number: H05K1/0216 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K3/242 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Layout methods for a substrate are disclosed. In one embodiment, the method includes: defining a first plating line on a non-conducting layer coupled to a first pad; and defining a second plating line on the first conducting layer coupled to a second pad. Along a direction away from the first pad and the second pad, a distance between the first plating line and the second plating line becomes longer. In another embodiment, the method includes: defining a plating line on a non-conducting layer, the plating line being coupled to a pad; and replacing a portion of at least a conducting layer with a non-conducting material, wherein the portion is directly under the plating line.

Abstract translation: 公开了一种用于衬底的布局方法。 在一个实施例中，该方法包括：在耦合到第一焊盘的非导电层上限定第一电镀线; 以及在耦合到第二焊盘的所述第一导电层上限定第二电镀线。 沿着远离第一焊盘和第二焊盘的方向，第一电镀线和第二镀覆线之间的距离变长。 在另一个实施例中，该方法包括：在非导电层上限定电镀线，电镀线耦合到焊盘; 以及用非导电材料代替至少导电层的一部分，其中该部分直接在电镀线下方。

公开(公告)号：US20070165389A1

公开(公告)日：2007-07-19

申请号：US11644892

申请日：2006-12-26

Applicant: Seung-young Ahn

Inventor： Seung-young Ahn

IPC: H05K7/12 ,  H05K7/10

CPC classification number: H05K1/0231 ,  H01P5/028 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/111 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/09727 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board assembly includes: a substrate; a main signal line formed on the substrate to transmit a signal; an SMD mounted on the substrate; a pad interposed between the SMD and the substrate; and a sub signal line provided on the substrate to electrically connect the main signal line with the pad, and having a width different from that of the main signal line. Thus, the printed circuit board assembly transmits a signal at a high speed and enhancing reliability and an economical efficiency of a product using the printed circuit board assembly.

Abstract translation: 印刷电路板组件包括：基板; 形成在基板上以传送信号的主信号线; 安装在基板上的SMD; 夹在SMD和衬底之间的衬垫; 以及设置在所述基板上的子信号线，以将所述主信号线与所述焊盘电连接，并且具有与所述主信号线的宽度不同的宽度。 因此，印刷电路板组件以高速度传输信号，并提高使用印刷电路板组件的产品的可靠性和经济效率。

公开(公告)号：US20070158797A1

公开(公告)日：2007-07-12

申请号：US11453163

申请日：2006-06-13

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/0792 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10931 ,  H05K2201/10969 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least one first pad and at least one second pad. The first pad has an extension part and is suitable for being electrically connected to the chip pad. The second pad is suitable for being electrically connected to one end of at least one of the inner leads, while the other end of the inner lead suitable for being electrically connected to the second pad has a projection at least partially overlapping the extension part on the patterned conductive layer. Moreover, the patterned conductive layer is disposed outside the insulating layer.

Abstract translation: 提供了适于电连接到芯片封装的电路板。 芯片封装具有芯片焊盘和多个内部引线。 电路板包括至少一个图案化导电层和至少一个绝缘层。 图案化导电层具有至少一个第一焊盘和至少一个第二焊盘。 第一焊盘具有延伸部分，并且适于电连接到芯片焊盘。 第二垫适于电连接到至少一个内引线的一端，而内引线的另一端适于与第二焊盘电连接，其突出部分至少部分地与第二焊盘上的延伸部分重叠 图案化导电层。 此外，图案化导电层设置在绝缘层的外部。

公开(公告)号：US07186927B2

公开(公告)日：2007-03-06

申请号：US10903534

申请日：2004-07-30

Applicant: John S Greeley

Inventor： John S Greeley

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01P1/047 ,  H05K1/0219 ,  H05K3/4046 ,  H05K3/42 ,  H05K2201/0792 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/10356 ,  H05K2201/10757

Abstract: A high frequency coax via structure is configured with a stripped semi-rigid cable (no shield), and an inductive compensation loop to mitigate transition discontinuity between that via structure's center conductor and the pad to which the center conductor is connected. The performance of top-to-bottom microwave transitions at high frequencies (e.g., 1 to 12 GHz) for such boards is enhanced. A non-metallized via hole embodiment that is configured with surrounding ground vias provides a greater degree of compensation for connection pads associated with greater capacitance (such as those coupled to a component).

Abstract translation: 高频同轴电缆通孔结构配置有剥离的半刚性电缆（无屏蔽）和电感补偿环路，以减轻该通孔结构的中心导体与中心导体所连接的焊盘之间的过渡不连续性。 在这种板的高频（例如，1至12GHz）上的顶部到底部的微波转换的性能得到提高。 配置有周围接地通孔的非金属化通孔实施例为与较大电容（例如耦合到部件的连接焊盘）相关联的连接焊盘提供更大程度的补偿。

公开(公告)号：US20060158784A1

公开(公告)日：2006-07-20

申请号：US11037753

申请日：2005-01-18

Applicant: Satya Arya ,  Xinzhi Xing

Inventor： Satya Arya ,  Xinzhi Xing

IPC: G11B17/00

CPC classification number: G11B5/486 ,  G11B5/4846 ,  G11B5/4853 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/056 ,  H05K1/111 ,  H05K2201/0792 ,  H05K2201/0969 ,  Y02P70/611

Abstract: An apparatus and method for extending a cover layer formation with respect to a solder pad portion on an electrical lead suspension (ELS). The method provides a base-metal layer for the ELS. A dielectric layer is also provided above the base-metal layer, the dielectric layer covering a portion of the base-metal layer. A signal conductive layer is provided above dielectric layer. The signal conductive layer carries at least one solder pad portion. A cover layer is also provided over the portions of the dielectric layer not having a solder pad portion thereon, the cover layer reducing the possibility of forming an unwanted electric bridge and reducing damage to the dielectric layer during a solder reflow process.

Abstract translation: 一种用于相对于电引线悬架（ELS）上的焊盘部分延伸覆盖层形成的装置和方法。 该方法为ELS提供了一个基础金属层。 介电层也设置在母金属层的上方，介电层覆盖基底金属层的一部分。 信号导电层设置在电介质层的上方。 信号导电层承载至少一个焊盘部分。 在绝缘层的不具有焊料焊盘部分的部分上还设有覆盖层，所述覆盖层减少了形成不需要的电桥的可能性，并减少了在回流焊过程中对电介质层的损坏。

公开(公告)号：US20060109033A1

公开(公告)日：2006-05-25

申请号：US10993777

申请日：2004-11-20

Applicant: Senthil Sundaram

Inventor： Senthil Sundaram

IPC: H03K5/22 ,  H03K5/153

CPC classification number: H05K1/0218 ,  H05G1/10 ,  H05K1/0254 ,  H05K1/18 ,  H05K2201/0792 ,  H05K2201/09781 ,  H05K2201/10022 ,  H05K2201/10553

Abstract: In some embodiments, a voltage grading and shielding method for a high voltage component, is provided. In some embodiments, the method includes configuring at least one first track constructed of a metal or an alloy, at a first location predetermined from the mounting position of the high voltage component, and at least one second track constructed of a metal or an alloy thereof, at a second location predetermined along the length of the high voltage component. In some embodiments, the configured at least one first track substantially reduces the stray capacitance effect and the at least one second track produces a substantially linear voltage distribution along the length of the high voltage component.

公开(公告)号：US20050218502A1

公开(公告)日：2005-10-06

申请号：US11090029

申请日：2005-03-28

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

IPC: H05K3/46 ,  H01L21/4763 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L25/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract translation: 在电容器安装的布线板中，以所需形状图案化的多个布线层被叠置在其间插入绝缘层，并且通过形成为在厚度方向上刺穿绝缘层的导体彼此连接。 去耦电容器电连接到用作布线层附近的电源线或接地线的布线层，并且安装成使得当电流通过电容器时，电流的方向被反转到 流过相关布线层的电流。

公开(公告)号：US20050136699A1

公开(公告)日：2005-06-23

申请号：US10742437

申请日：2003-12-19

Applicant: Kamran Amini ,  Joseph Diepenbrock ,  Robert Evans ,  Michael Scollard

Inventor： Kamran Amini ,  Joseph Diepenbrock ,  Robert Evans ,  Michael Scollard

IPC: H01R12/71 ,  H01R12/00 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/117 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/09672 ,  Y10S439/951

Abstract: A signal channel extends from motherboard to a daughter card across an edge connection. The daughter card includes a conductive plane that is held at a constant electrical potential. In order to compensate for a number of sources of inductance within the signal line at the edge connection, a circuit trace forming a portion of the signal channel includes an enlarged portion, spaced inward along the daughter card from the contact tabs forming the edge connection, that adds capacitive coupling of the signal channel with the conductive plane.

Abstract translation: 信号通道通过边缘连接从母板延伸到子卡。 子卡包括保持在恒定电位的导电平面。 为了补偿在边缘连接处的信号线中的多个电感源，形成信号通道的一部分的电路迹线包括沿着子卡从形成边缘连接的接触片向内间隔开的扩大部分， 这增加了信号通道与导电平面的电容耦合。

公开(公告)号：US20040070956A1

公开(公告)日：2004-04-15

申请号：US10269404

申请日：2002-10-11

Applicant: International Business Machines Corporation

Inventor： Rafael Antu ,  Cathy Marie Drews ,  David A. Plomgren ,  Todd Edward Takken

IPC: H05K001/18

CPC classification number: H05K1/0231 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133 ,  Y10T29/49165

Abstract: A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.

Abstract translation: 提供去耦电容的环路电感的方法和装置。 通风口移动靠近垫子并彼此靠近。 代替在电容器的相对侧上放置电源和接地通孔，这些通孔被移动到电容器的同一侧，并且如制造公差将允许的那样放置得彼此靠近。 对于使用标准两端表面贴装电容器的设计，每个电容器有两个通孔，以及标准制造程序（例如，焊盘内部没有通孔），提供了电容器与印刷电路板平面连接的最低环路电感。 这导致最低有效的电容器串联输入电感。

公开(公告)号：US06710266B2

公开(公告)日：2004-03-23

申请号：US10205725

申请日：2002-07-26

Applicant: Jason A. Mix ,  Yun Ling ,  Alok Tripathi ,  Kent E. Mallory

Inventor： Jason A. Mix ,  Yun Ling ,  Alok Tripathi ,  Kent E. Mallory

IPC: H05K111

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09309

Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.

Abstract translation: 公开了同时降低多层附加卡的高频插入损耗和串扰的技术。 该技术基于选择性地去除边缘手指下方的地面和电源平面。 电源和接地层的这种选择性去除消除了边缘手指处的过剩电容，降低了高频下的插入损耗，同时保持与相关连接器的阻抗匹配。 同时，剩余的金属接地/电源平面提供电磁屏蔽，从而减少差分对之间的串扰。 对于高速模拟和数字应用，可以获得具有最小插入损耗和串扰的连接器的最佳性能。