公开(公告)号：US08383952B2

公开(公告)日：2013-02-26

申请号：US12851014

申请日：2010-08-05

Applicant: Zhigang Wang ,  Vivek Subramanian ,  Lee Cleveland

Inventor： Zhigang Wang ,  Vivek Subramanian ,  Lee Cleveland

IPC: H05K1/00 ,  H05K3/12 ,  G06F17/50

CPC classification number: H05K3/0085 ,  G11C14/0054 ,  G11C17/14 ,  G11C17/18 ,  H01L23/5328 ,  H01L51/0022 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0296 ,  H05K1/16 ,  H05K3/125 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract translation: 本发明的实施例涉及与打印电子墨水，通过印刷电子墨水或印刷和常规覆盖层沉积和光刻的组合形成的印刷电路的电路布局，以及通过将电子墨水印刷到具有印刷的结构上形成电路的方法 兼容的形状。 布局包括具有（i）打印兼容形状和（ii）与布局中的每个其他特征的取向正交或平行的取向的特征。

公开(公告)号：US08358179B2

公开(公告)日：2013-01-22

申请号：US12557382

申请日：2009-09-10

Applicant: Robert C. Frye ,  Kai Liu

Inventor： Robert C. Frye ,  Kai Liu

IPC: H01P5/10 ,  H03H7/42

CPC classification number: H01L27/01 ,  H01L21/70 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01P5/10 ,  H03H7/48 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/165 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.

Abstract translation: 半导体器件具有在衬底上形成的衬底和RF耦合器。 RF耦合器具有第​​一导电迹线，其第一端耦合到半导体器件的第一端子，第二导电迹线具有耦合到半导体器件的第二端子的第一端。 第一导电迹线放置在第二导电迹线的第一部分附近。 在衬底上形成集成的无源器件。 第二导电迹线的第二部分用作集成无源器件的电路部件。 集成的无源器件可以是平衡 - 不平衡转换/低通滤波器。 RF耦合器还具有耦合到半导体器件的第一端子的第一电容器，并且耦合到半导体器件的第三端子的第二电容器用于更高的方向性。 第二导电迹线被卷绕以呈现感应特性。

公开(公告)号：US08357013B2

公开(公告)日：2013-01-22

申请号：US12613501

申请日：2009-11-05

Applicant: Tatsuya Arai ,  Ching-Chao Huang ,  Clement Kam Lam Luk ,  Jeremy Buan ,  Tsutomu Matsuo ,  Toshiyuki Takada ,  Masakazu Nagata

Inventor： Tatsuya Arai ,  Ching-Chao Huang ,  Clement Kam Lam Luk ,  Jeremy Buan ,  Tsutomu Matsuo ,  Toshiyuki Takada ,  Masakazu Nagata

IPC: H01R24/00

CPC classification number: H04M1/76 ,  H05K1/0245 ,  H05K2201/09245 ,  H05K2201/10689

Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Abstract translation: 本发明涉及通过使用新的极性交换来减少FEXT的累积效应来减少远端串扰（FEXT）的连接器。 倾斜调整用于改善极性交换中的FEXT消除。 FEXT源中的极性反转位置或位置被优化，以实现最大的FEXT取消。 新颖的极性交换技术可以应用于各种连接器，例如夹层连接器，背板连接器以及可以从FEXT减少中受益的任何其他连接器。

公开(公告)号：US08253672B2

公开(公告)日：2012-08-28

申请号：US12186348

申请日：2008-08-05

Applicant: Sung-Kyu Lee ,  On-Sik Choi ,  Do-Wan Kim ,  Sung-Wook Kang

Inventor： Sung-Kyu Lee ,  On-Sik Choi ,  Do-Wan Kim ,  Sung-Wook Kang

IPC: H01L23/04

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/097

Abstract: One or more embodiments of the present disclosure relate to a circuit board having a substrate and a plurality of differential signal lines formed on the substrate and transmitting differential signals. The differential signal lines include a first signal line and a second signal line. The first signal line and the second signal line extend along at least two paths that are parallel to each other. The paths of the first signal line and the second signal line switch at path change portions, and the path change portions of neighboring differential signal lines are positioned at different distances away from an edge of the circuit board along the length direction of the differential signal line.

Abstract translation: 本公开的一个或多个实施例涉及具有衬底和形成在衬底上并传输差分信号的多个差分信号线的电路板。 差分信号线包括第一信号线和第二信号线。 第一信号线和第二信号线沿着彼此平行的至少两个路径延伸。 第一信号线和第二信号线开关在路径改变部分的路径，并且相邻差分信号线的路径变化部分位于与差分信号线的长度方向上离电路板边缘不同的距离处 。

公开(公告)号：USRE43510E1

公开(公告)日：2012-07-17

申请号：US12793052

申请日：2010-06-03

Applicant: Luc Adriaenssens ,  Amid Hashim ,  Troy Long

Inventor： Luc Adriaenssens ,  Amid Hashim ,  Troy Long

IPC: H05K1/00

CPC classification number: H01R13/6466 ,  H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.

Abstract translation: 提供连接器，用于当使用低串扰插头时同时提高NEXT高频性能，并且当使用高串扰插头时NEXT低频性能。 连接器包括由具有不同介电频率特性的材料制成的PCB衬底。

公开(公告)号：US20120103677A1

公开(公告)日：2012-05-03

申请号：US13345352

申请日：2012-01-06

Applicant: Satoshi YAMAMOTO ,  Hirokazu HASHIMOTO

Inventor： Satoshi YAMAMOTO ,  Hirokazu HASHIMOTO

IPC: H05K1/11 ,  B05D3/06 ,  H05K3/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0272 ,  H05K1/115 ,  H05K3/101 ,  H05K3/42 ,  H05K2201/09245 ,  H05K2201/09845 ,  H05K2201/09981 ,  H01L2924/00

Abstract: A through wiring substrate includes a substrate including a first face and a second face, and a plurality of through-wires formed by filling, or forming a film of, an electrically-conductive substance in through-holes that penetrate between the first face and the second face. The through-wires are separated from each other, and, include at least one overlap section in a plan view of the substrate.

Abstract translation: 通过布线基板包括具有第一面和第二面的基板，以及在通孔内填充或形成导电性物质的膜而形成的多条贯通丝，该通孔贯穿第一面和第 第二面。 通线彼此分离，并且在基板的平面图中包括至少一个重叠部分。

公开(公告)号：US20110318965A1

公开(公告)日：2011-12-29

申请号：US13222854

申请日：2011-08-31

Applicant: BERNARD HAROLD HAMMOND, JR. ,  DAVID PATRICK MURRAY ,  IAN ROBERT GEORGE

Inventor： BERNARD HAROLD HAMMOND, JR. ,  DAVID PATRICK MURRAY ,  IAN ROBERT GEORGE

IPC: H01R13/66

CPC classification number: H01R13/6466 ,  H01R4/2416 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49117 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

Abstract translation: 本公开涉及一种电信插孔，其包括具有用于接收插头的端口的壳体。 千斤顶还包括多个接触弹簧，其适于当插头插入壳体的端口时与插头电接触，以及多个用于将插线端接到插座的导线终端触头。 千斤顶还包括将接触弹簧电连接到导线终端触点的电路板。 电路板包括用于减少插座处串扰的多区串扰补偿装置。

公开(公告)号：US20110298739A1

公开(公告)日：2011-12-08

申请号：US13152805

申请日：2011-06-03

Applicant: Ming-Kung WU ,  Kuo-Chang SU ,  Chia-Chi CHEN ,  Yu-Ting LIN

Inventor： Ming-Kung WU ,  Kuo-Chang SU ,  Chia-Chi CHEN ,  Yu-Ting LIN

IPC: G06F3/041

CPC classification number: H03K17/9618 ,  G02B1/11 ,  G06F1/1643 ,  G06F1/1692 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/044 ,  G06F3/047 ,  H01H11/00 ,  H03K2017/9602 ,  H05K1/0296 ,  H05K1/0306 ,  H05K2201/0326 ,  H05K2201/09245 ,  H05K2201/10128 ,  H05K2201/10151 ,  Y10T29/49105

Abstract: A touch-sensitive device includes a transparent substrate, a touch-sensing structure, a decorative layer, a trace layer, a passivation layer and a sheltering layer. The touch-sensing structure is disposed on the transparent substrate and located in a touch-sensitive region. The decorative layer is disposed on the transparent substrate and located in a non-touch-sensitive region, and the trace layer is disposed on the decorative layer. The passivation layer is disposed on the transparent substrate and at least covers the touch-sensing structure and the trace layer. The sheltering layer is disposed at least on the passivation layer and located in the non-touch-sensitive region.

Abstract translation: 触敏装置包括透明基板，触摸感测结构，装饰层，迹线层，钝化层和遮蔽层。 触摸感测结构设置在透明基板上并且位于触敏区域中。 装饰层设置在透明基板上并且位于非触敏区域中，并且迹线层设置在装饰层上。 钝化层设置在透明基板上，并且至少覆盖触摸感测结构和迹线层。 防护层至少设置在钝化层上并且位于非接触敏感区域中。

公开(公告)号：US08054643B2

公开(公告)日：2011-11-08

申请号：US12320641

申请日：2009-01-30

Applicant: Wataru Tsukada

Inventor： Wataru Tsukada

IPC: H05K7/02

CPC classification number: H05K1/181 ,  H05K2201/09245 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.

Abstract translation: 半导体模块包括多个矩形半导体器件，它们被布置成两行，使得每对相邻的半导体器件的取向彼此相差90度。 多个布线将包括在两行之一中的半导体器件连接到另一行中包括的半导体器件，使得以相同取向排列的半导体器件彼此连接。

公开(公告)号：US08026448B2

公开(公告)日：2011-09-27

申请号：US12068169

申请日：2008-02-04

Applicant: Koichi Tanaka

Inventor： Koichi Tanaka

IPC: H05K1/03

CPC classification number: H05K3/462 ,  H05K1/0289 ,  H05K3/4647 ,  H05K2201/09245 ,  H05K2203/0733 ,  H05K2203/1327 ,  Y10T29/49126

Abstract: A multilayer wiring board includes at least two wiring boards having wiring layers containing wiring patterns formed on both sides. A pair of fin-shaped bumps are formed at desired positions on wiring patterns on the surfaces facing each other, of the wiring boards, so that the bumps assume a slender shape as seen in plan view and that the bumps intersect each other. The pair of fin-shaped bumps are electrically connected to form an inter-board connection terminal. Further, an insulating layer is formed between the wiring boards, and protection films are formed to cover the entire surface except pad areas defined at predetermined positions on outer wiring layers of the wiring boards.

Abstract translation: 多层布线基板包括至少两个布线板，布线层包含形成在两侧的布线图案。 在布线板的彼此相对的表面上的布线图案的期望位置处形成一对鳍状凸起，使得凸起呈现如平面图中看到的细长形状，并且凸块彼此相交。 一对鳍状凸块电连接以形成板间连接端子。 此外，在布线板之间形成绝缘层，并且形成保护膜以覆盖限定在布线板的外部布线层上的预定位置处的焊盘区域之外的整个表面。