公开(公告)号：US11837463B2

公开(公告)日：2023-12-05

申请号：US17095550

申请日：2020-11-11

Applicant: Soitec

Inventor： Pascal Guenard ,  Marcel Broekaart ,  Thierry Barge

IPC: H01L21/02 ,  H10N30/50 ,  H10N30/072 ,  H10N30/853 ,  H03H9/02

CPC classification number: H01L21/02002 ,  H01L21/02367 ,  H01L21/02436 ,  H10N30/072 ,  H10N30/50 ,  H10N30/8542 ,  H03H9/02574

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

公开(公告)号：US11828000B2

公开(公告)日：2023-11-28

申请号：US17042737

申请日：2019-03-26

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: C30B25/18 ,  C30B29/30 ,  C30B33/06 ,  H01L21/762

CPC classification number: C30B25/183 ,  C30B29/30 ,  C30B33/06 ,  H01L21/76254

Abstract: A process for producing a monocrystalline layer of LNO material comprises the transfer of a monocrystalline seed layer of YSZ material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material.

公开(公告)号：US20230366755A1

公开(公告)日：2023-11-16

申请号：US18246081

申请日：2021-09-29

Applicant: Soitec

Inventor： Emilie Courjon ,  Florent Bernad ,  Thierry LaRoche ,  Julien Garcia ,  Alexandre Clairet ,  Sylvain Ballandras

IPC: G01L1/16

CPC classification number: G01L1/162

Abstract: A resonator device for measuring stress comprises at least two resonators, each resonator comprising an inter-digitated transducer structure arranged between two reflecting structures on or in a piezoelectric substrate, wherein the at least two resonators are arranged and positioned such that they have two different wave propagation directions, and each resonator comprises at least two parts with the area between the two parts of the at least two resonators forming a cavity, wherein the cavity is shared by the at least two resonators and wherein for at least one resonator, in particular, all resonators, the inter-digitated transducer structure comprises a first material and the reflecting structures a second material different from the first material and/or the inter-digitated transducer structure and the reflecting structures have different geometrical parameters. A differential sensing device comprises at least one resonator device as described herein.

公开(公告)号：US20230292618A1

公开(公告)日：2023-09-14

申请号：US18322433

申请日：2023-05-23

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: H10N30/20 ,  H10N30/01

CPC classification number: H10N30/2047 ,  H10N30/01 ,  B06B1/0292

Abstract: A design process is used for designing a device comprising a plurality of micro-machined elements, each comprising a flexible membrane, the elements being arranged in a plane in a determined topology. The design process comprises a step of defining the determined topology so that it has a character compatible with a generic substrate having cavities, the characteristics of which are pre-established. Each flexible membrane of the micro-machined elements is associated with one cavity of the generic substrate. The present disclosure also relates to a fabrication process for fabricating a device comprising a plurality of micro-machined elements, and to this device itself, wherein only some of the pairs of cavities and flexible membranes are configured to form a set of functional micro-machined elements.

公开(公告)号：US20230275559A1

公开(公告)日：2023-08-31

申请号：US18302440

申请日：2023-04-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H10N30/072 ,  H10N30/073 ,  H10N30/00 ,  H10N30/853 ,  H03H3/10

CPC classification number: H03H9/02834 ,  H03H9/02574 ,  H03H3/04 ,  H10N30/072 ,  H10N30/073 ,  H10N30/1051 ,  H10N30/8542 ,  H03H3/10 ,  Y10T29/42 ,  H10N30/082

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20230244095A1

公开(公告)日：2023-08-03

申请号：US18003387

申请日：2021-06-22

Applicant: Soitec

Inventor： Corrado Sciancalepore ,  Bruno Ghyselen ,  Alain Delpy ,  Céline Cailler ,  David Herisson ,  Aziz Alamidrissi

IPC: G02F1/01

CPC classification number: G02F1/0147 ,  G02F1/011 ,  G02F2202/105

Abstract: A method for manufacturing a thermo-optic component comprises the following steps:



a) providing a silicon-on-insulator (SOI) substrate comprising:

a surface layer made of single-crystal silicon, extending in a main plane and placed on a dielectric layer, itself placed on a carrier made of silicon, and
at least one buried cavity, which is formed in the carrier and which opens under the dielectric layer,


b) forming an optical waveguide extending in the main plane and comprising a core formed in the surface layer and encircled by an optical confinement layer including the dielectric layer,
c) producing at least one heating element, on the optical waveguide, the heating element being positioned, in the main plane, plumb with a segment of the optical waveguide, or on either side of the segment, the heating element and the segment of the optical waveguide being located plumb with the at least one recessed buried cavity.

公开(公告)号：US11711065B2

公开(公告)日：2023-07-25

申请号：US17141065

申请日：2021-01-04

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: A61B5/1459 ,  A61B5/00 ,  A61B5/145 ,  H03H9/02 ,  H03H3/02 ,  H10N30/072 ,  H10N30/87 ,  H10N39/00 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H10N30/085

CPC classification number: H03H9/02834 ,  A61B5/1459 ,  A61B5/14546 ,  A61B5/685 ,  H03H3/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/02102 ,  H03H9/02574 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/6489 ,  H10N30/072 ,  H10N30/87 ,  H10N39/00 ,  A61B2562/0204 ,  H03H2003/0407 ,  H10N30/085

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20230207382A1

公开(公告)日：2023-06-29

申请号：US17998833

申请日：2021-05-18

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Walter Schwarzenbach ,  Frédéric Allibert

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A method for fabricating a semiconductor-on-insulator substrate for radiofrequency applications, comprises:



forming a donor substrate through epitaxial growth of an undoped semiconductor layer on a p-doped semiconductor seed substrate;
forming an electrically insulating layer on the undoped epitaxial semiconductor,
implanting ion species through the electrically insulating layer, so as to form, in the undoped epitaxial semiconductor layer, a weakened area defining a semiconductor thin layer to be transferred,
providing a semiconductor carrier substrate having an electrical resistivity greater than or equal to 500 Ω·cm,
bonding the donor substrate to the carrier substrate via the electrically insulating layer, and
detaching the donor substrate along the weakened area of embrittlement so as to transfer the semiconductor thin layer from the donor substrate to the carrier substrate.

公开(公告)号：US20230197435A1

公开(公告)日：2023-06-22

申请号：US17907517

申请日：2021-01-12

Applicant: Soitec

Inventor： Hugo Biard

IPC: H01L21/02 ,  C30B1/02 ,  C30B29/36 ,  C23C14/48 ,  C30B25/18 ,  C30B33/10 ,  C23C16/32 ,  C23C16/01

CPC classification number: H01L21/02002 ,  H01L21/02079 ,  C30B1/023 ,  C30B29/36 ,  C23C14/48 ,  C30B25/18 ,  C30B33/10 ,  C23C16/325 ,  C23C16/01

Abstract: A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline silicon carbide, b) a step of ion implantation of light species into the donor substrate, to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate, c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2; the n crystalline carrier layers being positioned on the front face of the donor substrate successively one on the other, and forming the carrier substrate; each formation step comprising: direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; d) a step of separation along the buried brittle plane, to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the rest of the donor substrate.

公开(公告)号：US11670540B2

公开(公告)日：2023-06-06

申请号：US17190004

申请日：2021-03-02

Applicant: Soitec ,  COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

Inventor： Didier Landru ,  Nadia Ben Mohamed ,  Oleg Kononchuk ,  Frédéric Mazen ,  Damien Massy ,  Shay Reboh ,  François Rieutord

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/263

CPC classification number: H01L21/76254 ,  H01L21/263 ,  H01L21/324 ,  H01L21/76251

Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.