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    Method of fabricating dual damascene structure
    171.
    发明授权
    Method of fabricating dual damascene structure 有权

    公开(公告)号：US09748139B1

    公开(公告)日：2017-08-29

    申请号：US15016230

    申请日：2016-02-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

    IPC: H01L21/768

    CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2221/1021

    Abstract: A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second dielectric layer and the hard mask layer. A first photoresist pattern with a first trench opening above the partial via and a second trench opening is formed on the hard mask layer. The hard mask layer and the second dielectric layer are etched through the first trench opening and the second trench opening, thereby forming a first dual damascene structure comprising a first trench and a first via, and a second trench in the second dielectric layer, respectively. A second photoresist pattern having a self-aligned via opening above the second trench is formed. The second dielectric layer is etched through the self-aligned via opening, thereby forming a second dual damascene structure comprising the second trench and a second via under the second trench.

    METHOD OF ADJUSTING CHANNEL WIDTHS OF SEMICONDUCTIVE DEVICES
    175.
    发明申请
    METHOD OF ADJUSTING CHANNEL WIDTHS OF SEMICONDUCTIVE DEVICES 有权
    调整半导体器件通道宽度的方法

    公开(公告)号：US20170025286A1

    公开(公告)日：2017-01-26

    申请号：US14809270

    申请日：2015-07-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Te Chen ,  Chia-Hsun Tseng ,  En-Chiuan Liou ,  Chiung-Lin Hsu ,  Meng-Lin Tsai ,  Jan-Fu Yang ,  Yu-Ting Hung ,  Shin-Feng Su

    IPC: H01L21/321 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/225

    CPC classification number: H01L21/2253 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821

    Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

    Abstract translation: 调整半导体器件的沟道宽度的方法包括提供分成第一区域和第二区域的衬底，其中衬底包括多个鳍片。 在第一区域内的翅片上执行第一注入工艺。 然后，对第二区域内的翅片执行第二注入工艺，其中第一注入工艺和第二注入工艺在包括掺杂剂种类，掺杂剂剂量或注入能量的至少一个条件中彼此不同。 之后，同时去除第一区域和第二区域内的部分散热片，以在第一区域内形成多个第一凹槽，在第二区域内形成多个第二凹槽。 最后，形成第一外延层和第二外延层以分别填充每个第一凹槽和每个第二凹槽。

    Semiconductor device and manufacturing methods thereof
    178.
    发明授权
    Semiconductor device and manufacturing methods thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09530851B1

    公开(公告)日：2016-12-27

    申请号：US14841661

    申请日：2015-08-31

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L29/42364 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7843

    Abstract: The present invention provides a semiconductor device, including at least two gate structures, and each gate structure includes a gate, a spacer and a source/drain region, the source/drain region disposed on two sides of the gate. A first dielectric layer is disposed on the substrate and between two gate structures, where the first dielectric layer has a concave surface, and the first dielectric layer directly contacts the spacer. A floating spacer is disposed on the first dielectric layer and on a sidewall of the gate, and at least one contact plug is disposed on the source/drain region, where the contact plug directly contacts the floating spacer.

    Abstract translation: 本发明提供一种包括至少两个栅极结构的半导体器件，并且每个栅极结构包括栅极，间隔物和源极/漏极区域，源极/漏极区域设置在栅极的两侧。 第一电介质层设置在衬底上并且在两个栅极结构之间，其中第一电介质层具有凹面，并且第一电介质层直接接触间隔物。 浮动间隔物设置在第一介电层上和栅极的侧壁上，并且至少一个接触插塞设置在源极/漏极区上，其中接触插塞直接接触浮动间隔物。

    Semiconductor process for forming gates with different pitches and different dimensions
    179.
    发明授权
    Semiconductor process for forming gates with different pitches and different dimensions 有权
    用于形成具有不同节距和不同尺寸的门的半导体工艺

    公开(公告)号：US09525041B2

    公开(公告)日：2016-12-20

    申请号：US14621358

    申请日：2015-02-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

    IPC: H01L21/311 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

    CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66553

    Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

    Abstract translation: 用于形成具有不同间距的门的半导体工艺包括以下步骤。 栅极层形成在基板上。 第一心轴和第二心轴分别形成在栅极层上。 形成第一间隔材料以保形地覆盖第一心轴但暴露第二心轴。 形成第二间隔材料以共形地覆盖第一间隔物材料和第二心轴。 蚀刻第一间隔物材料和第二间隔物材料以在第一心轴旁边形成第一间隔物，同时在第二心轴旁边形成第二间隔物。 去除第一心轴和第二心轴。 第一间隔物和第二间隔物的布置被转移到栅极层，从而形成第一栅极和第二栅极。 此外，还提供了分别形成第一间隔件和第二间隔件的半导体工艺。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    180.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20160336187A1

    公开(公告)日：2016-11-17

    申请号：US14737507

    申请日：2015-06-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

    IPC: H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431

    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a plurality of mandrels is formed on a target layer. Next, a plurality of first liner is formed adjacent to two sides of the mandrels. Then, a plurality of second liners is formed adjacent to two sides of the first liners. After these, a plurality of third liners is formed adjacent to two sides of the second liners. Finally, the mandrels and the second liners are simultaneously removed.

    Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，在目标层上形成多个心轴。 接下来，与心轴的两侧相邻地形成多个第一衬垫。 然后，与第一衬垫的两侧相邻地形成多个第二衬垫。 之后，与第二衬垫的两侧相邻地形成多个第三衬垫。 最后，心轴和第二衬垫被同时移除。

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