公开(公告)号：US08461035B1

公开(公告)日：2013-06-11

申请号：US12894235

申请日：2010-09-30

Applicant: Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zvi Or-Bach

Inventor： Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L21/44 ,  H01L21/82

CPC classification number: H01L21/76898 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/082 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/785 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors wherein the first transistors include mono-crystalline semiconductor and first alignment marks; overlaying a second semiconductor layer over the first layer, wherein the second layer includes second transistors, the second transistors include mono-crystalline semiconductor and are configured to be memory cells, at least one of the memory cells include a floating body region configured to be charged to a level indicative of a state of the memory cell, and fabricating the second transistors includes alignment to the first alignment marks.

Abstract translation: 一种制造器件的方法，所述方法包括：提供包括第一晶体管的第一层，其中所述第一晶体管包括单晶半导体和第一对准标记; 在所述第一层上覆盖第二半导体层，其中所述第二层包括第二晶体管，所述第二晶体管包括单晶半导体，并且被配置为存储器单元，所述存储器单元中的至少一个包括配置为被充电的浮体区域 到指示存储单元的状态的电平，并且制造第二晶体管包括与第一对准标记对准。

公开(公告)号：US08450804B2

公开(公告)日：2013-05-28

申请号：US13571614

申请日：2012-08-10

Applicant: Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L23/3677 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/12 ,  H01L29/785 ,  H01L2027/11812 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

Abstract translation: 一种器件，包括：由至少一个互连层覆盖的第一晶体管层，其中所述互连层包括诸如铜或铝的金属; 包括第二晶体管的第二层，所述第二层覆盖所述互连层，其中所述第二层小于约0.4微米厚; 以及将所述第二晶体管连接到所述互连层的连接路径，其中所述连接路径包括至少一个通孔，并且所述贯通层通孔包括其热膨胀系数在所述第二层的约50％内的材料 热膨胀系数。

公开(公告)号：US08390326B2

公开(公告)日：2013-03-05

申请号：US12782448

申请日：2010-05-18

Applicant: Zvi Or-Bach ,  James M. Tour ,  Jun Yao ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  James M. Tour ,  Jun Yao ,  Brian Cronquist

IPC: H03K19/177

CPC classification number: H01L23/5252 ,  H01L23/53276 ,  H01L27/11803 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H03K19/17796 ,  H01L2924/00

Abstract: Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Additionally, the re-programmable antifuses may be configured to a permanently conductive state by applying an even higher voltage across it.

Abstract translation: 本文介绍了使用可重新编程反熔丝的可重新编程反熔丝和结构。 这种结构包括具有至少一个可再编程反熔丝的可配置互连电路，其中所述至少一个可再编程反熔丝被配置为通过在其上施加第一电压而被编程为进行导通，并被配置为被重新编程为不进行 通过在其上施加第二电压，其中第二电压高于第一电压。 此外，重编程反熔丝可以通过在其上施加更高的电压而被配置为永久导通状态。

公开(公告)号：US08378494B2

公开(公告)日：2013-02-19

申请号：US13162154

申请日：2011-06-16

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L23/58 ,  H01L23/528 ,  H01L21/98

CPC classification number: H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Abstract translation: 一种半导体器件，包括：第一单晶硅层，包括第一晶体管，第一对准标记和覆盖所述第一单晶硅层的至少一个金属层，其中所述至少一个金属层比其它材料包含铜或铝; 覆盖所述至少一个金属层的第二层，所述第二层包括第二晶体管，第二对准标记和穿过所述第二层的通孔，其中所述通孔是所述第一晶体管和所述第二晶体管之间的连接路径的一部分 ，其中所述通孔的对准基于所述第一对准标记和所述第二对准标记，并且受到所述第一对准标记和所述第二对准标记之间的距离的影响。

公开(公告)号：US08373230B1

公开(公告)日：2013-02-12

申请号：US12904114

申请日：2010-10-13

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L27/12

CPC classification number: H01L21/76254 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/6835 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L23/535 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are disclosed for fabricating a semiconductor device, includes implanting one or more regions on a semiconductor wafer; performing a layer transfer onto a carrier; and transferring from said carrier to a target wafer.

Abstract translation: 公开了用于制造半导体器件的系统和方法，包括在半导体晶片上注入一个或多个区域; 执行层转移到载体上; 并从所述载体转移到目标晶片。

公开(公告)号：US08237228B2

公开(公告)日：2012-08-07

申请号：US13246384

申请日：2011-09-27

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/092

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract translation: 系统包括半导体器件。 该半导体器件包括包括第一晶体管的第一半导体层，其中第一晶体管通过包括铝或铜的至少一个金属层互连。 第二单结晶半导体层包括第二晶体管并且覆盖至少一个金属层，其中第二单结晶半导体层的厚度小于150nm，并且至少一个第二晶体管是N型晶体管 并且所述第二晶体管中的至少一个是P型晶体管。

公开(公告)号：US20120107967A1

公开(公告)日：2012-05-03

申请号：US13314435

申请日：2011-12-08

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/768 ,  H01L21/98 ,  H01L21/00

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including first transistors and interconnecting metal layers to perform at least one first electronic function; providing a second monocrystalline layer on top of the metal layers, wherein the second monocrystalline layer includes second transistors to perform at least one second electronic function and substituting the at least one first electronic function with the at least one second electronic function.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括第一晶体管和互连金属层的第一单晶层，以执行至少一个第一电子功能; 在所述金属层的顶部上提供第二单晶层，其中所述第二单晶层包括执行至少一个第二电子功能的第二晶体管，并用所述至少一个第二电子功能代替所述至少一个第一电子功能。

公开(公告)号：US20110199116A1

公开(公告)日：2011-08-18

申请号：US12706520

申请日：2010-02-16

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Zeev Wurman ,  Israel Beinglass ,  J. L. de Jong

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Zeev Wurman ,  Israel Beinglass ,  J. L. de Jong

IPC: H03K19/173 ,  H01L23/538 ,  H01L21/306 ,  H01L21/26 ,  H01L21/70

CPC classification number: H01L21/76254 ,  H01L21/76232 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.

Abstract translation: 一种可配置设备，包括通过至少一个通过硅通孔（TSV）连接到输入/输出（I / O）管芯的逻辑管芯。

公开(公告)号：US20100291749A1

公开(公告)日：2010-11-18

申请号：US12847911

申请日：2010-07-30

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC: H01L21/77 ,  H01L21/027

CPC classification number: G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用基于所述第一对准标记和所述第二对准标记之间的未对准的对准来执行光刻。

公开(公告)号：US20100289064A1

公开(公告)日：2010-11-18

申请号：US12849272

申请日：2010-08-03

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC: H01L23/522

CPC classification number: H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Abstract translation: 一种半导体器件，包括：包含第一晶体管，第一对准标记和覆盖在第一单晶硅层上的至少一个金属层的第一单晶硅层，其中所述至少一个金属层比其它材料包括铜或铝; 以及覆盖所述至少一个金属层的第二单晶硅层; 其中所述第二单晶硅层包括以基本上平行的带布置的多个第二晶体管，其中所述多个所述带中的每一个包括沿重复图案的轴的所述第二晶体管的一部分。