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    Method of fabricating an LC panel
    11.
    发明授权
    Method of fabricating an LC panel 失效
    制造LC面板的方法

    公开(公告)号：US06669520B2

    公开(公告)日：2003-12-30

    申请号：US09682550

    申请日：2001-09-19

    Applicant: Chin-Lung Hung ,  Charlie Han ,  Wei-Hsiao Chen

    Inventor： Chin-Lung Hung ,  Charlie Han ,  Wei-Hsiao Chen

    IPC: H01J924

    CPC classification number: G02F1/13394

    Abstract: A backplane with multiple arrayed electrodes positioned on the backplane is provided in a method of fabricating a liquid crystal (LC) panel. The method begins with coating an alignment layer on the backplane. By performing a rubbing process, multiple alignment trenches are formed on the alignment layer. A photoresist layer is then formed on the alignment layer. By performing a lithography process, both a side frame, having at least one slit, and multiple photoresist spacers(PR spacers) are formed on the alignment layer. A gasket seal is coated on the side frame and the multiple PR spacers. By performing a lamination process, a transparent conductive layer is laminated on the backplane. A liquid crystal filling (LC filling) processis then performed to fill a cell gap between the backplane and the transparent conductive layer with liquid crystal. Finally, an end sealing process is performed to seal the slit.

    Abstract translation: 在制造液晶（LC）面板的方法中提供了设置在背板上的多个阵列电极的背板。 该方法开始于在背板上涂覆取向层。 通过进行摩擦处理，在取向层上形成多个取向沟。 然后在对准层上形成光致抗蚀剂层。 通过进行光刻处理，在取向层上形成具有至少一个狭缝的侧框架和多个光刻胶间隔物（PR间隔物）。 垫片密封件涂覆在侧框架和多个PR垫片上。 通过进行层压处理，在背板上层叠透明导电层。 然后进行液晶填充（LC填充）处理以用液晶填充背板和透明导电层之间的单元间隙。 最后，进行封口处理以密封狭缝。

    Placement and routing for wafer scale memory
    12.
    发明授权
    Placement and routing for wafer scale memory 失效
    硅片刻度存储器的放置和布线

    公开(公告)号：US06512708B1

    公开(公告)日：2003-01-28

    申请号：US09981650

    申请日：2001-10-16

    Applicant: Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

    Inventor： Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

    IPC: G11V700

    CPC classification number: H01L22/22 ,  G06F17/5068 ,  G11C11/4097 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals. During fabrication, the replacement of defective chips with spare chips is accomplished by using two extra conductive layers and patterning the extra layers using a mask that is independent of the defect distribution of a particular wafer.

    Abstract translation: 用于晶片刻度存储器和放置方法的架构用存储器模块中的备用芯片代替有缺陷的芯片，以便提供最小临界信号延迟。 SDRAM存储器芯片被分为正常芯片和备用芯片，其中普通芯片形成为诸如行或列的组，并且备用芯片用于替换有缺陷的普通芯片。 金属线和通孔的延迟模型用于计算放置和布线的信号延迟。 放置问题被建模为二分图，并使用分支和约束算法来求解具有最短关键信号延迟的芯片替换配置。 还描述了分级路由方法，其将信号分类成不同类型和级别的信号。 在制造期间，通过使用两个额外的导电层并且使用独立于特定晶片的缺陷分布的掩模对附加层进行图案化来实现用备用芯片替换有缺陷的芯片。

    Circuit for burn-in operation on a wafer of memory devices
    15.
    发明授权
    Circuit for burn-in operation on a wafer of memory devices 失效
    存储器件晶圆上的老化操作电路

    公开(公告)号：US5995428A

    公开(公告)日：1999-11-30

    申请号：US32627

    申请日：1998-02-27

    Applicant: Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    Inventor： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    IPC: G01R31/28 ,  G11C29/50 ,  G11C29/00

    CPC classification number: G11C29/50 ,  G01R31/2856 ,  G11C11/401

    Abstract: A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

    Abstract translation: 提供了一种电路，用于在形成有多个骰子的晶片上使用，每个骰子具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过该电路，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

    Coolant service monitoring system
    16.
    发明申请
    Coolant service monitoring system 审中-公开
    冷却液服务监控系统

    公开(公告)号：US20050034510A1

    公开(公告)日：2005-02-17

    申请号：US10638462

    申请日：2003-08-12

    Applicant: Charlie Han

    Inventor： Charlie Han

    IPC: F01P11/06 ,  F01P11/14 ,  G01N33/00 ,  G01N27/27 ,  G01N31/00

    CPC classification number: F01P11/14 ,  F01P2011/066 ,  F01P2025/00 ,  F01P2025/80 ,  F01P2031/00

    Abstract: Engine coolant and its related components is a vital fluid in any internal combustion engine, however it is one of the most neglected systems in the vehicle. The newest domestic automobiles do not have service indicators for engine coolant; which would allow the owner to service the fluid before any serious damage occurs from electrolysis and metal breakdown. The proposed Coolant Service Monitoring System (CSMS) will utilize sensors to monitor the pH of the coolant mixture, as well as the DC voltage of the coolant with respect to ground. By monitoring the pH and voltage, the sensors can notify the operator when unsafe coolant conditions are present. Ultimately, by preventing excessive corrosion and accelerated electrolysis, automobile owners can save hundreds if not thousands of dollars by not having to replace heater cores, expensive radiators, and water pumps with the CSMS implemented in the vehicle.

    Abstract translation: 发动机冷却液及其相关组件是任何内燃机中重要的流体，但它是车辆中被忽视的系统之一。 国内最新的汽车没有发动机冷却液的服务指标; 这将允许业主在电解和金属破坏发生严重损坏之前对流体进行维修。 所提出的冷却液服务监控系统（CSMS）将利用传感器来监测冷却剂混合物的pH以及冷却剂相对于地面的直流电压。 通过监测pH和电压，当不安全的冷却液条件存在时，传感器可以通知操作员。 最终，通过防止过度腐蚀和加速电解，汽车业主可以通过在车辆中实施CSMS而不必更换加热器芯，昂贵的散热器和水泵来节省数百甚至数千美元。

    Alternate timing wafer burn-in method
    18.
    发明授权
    Alternate timing wafer burn-in method 有权
    替代定时晶片老化方法

    公开(公告)号：US06388460B1

    公开(公告)日：2002-05-14

    申请号：US09698713

    申请日：2000-10-27

    Applicant: Walx Fang ,  Charlie Han

    Inventor： Walx Fang ,  Charlie Han

    IPC: G01F3102

    CPC classification number: G01R31/318511 ,  G01R31/2879 ,  G01R31/318505 ,  G11C29/006 ,  G11C29/56012 ,  G11C2029/1204

    Abstract: An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.

    Abstract translation: 一种适用于测试晶片上的多个存储器单元并且能够防止由于直流定时引起的空转的替代定时老化方法。 产生第一位线电压计时信号并将其发送到任何存储器单元的一个端子。 产生第二位线电压时钟信号并将其发送到同一存储器单元的另一端。 此外，第二位线电压计时信号的边沿对应于第一位线电压计时信号的中点。

    Cascade-type chip module
    20.
    发明授权
    Cascade-type chip module 有权
    级联型芯片模块

    公开(公告)号：US6166444A

    公开(公告)日：2000-12-26

    申请号：US337708

    申请日：1999-06-21

    Applicant: Min-Chih Hsuan ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Charlie Han

    IPC: H01L25/065 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L29/40

    CPC classification number: H01L25/0652 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/013

    Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group. The chips are coupled to each other by bumps. The chips are attached to the laminate substrate and the first group and the second group are respectively coupled with the contacts by two film carriers.

    Abstract translation: 级联型芯片模块。 提供具有触点的层叠基板。 提供了适用于级联型模块的芯片。 每个芯片包括具有第一区域和第二区域的再分配层，并且凸块接触再分布层上方。 与再分布层的第一区域耦合的突起触点的布局是与再分布层的第二区域耦合的布局的布局旋转对称的图像，并且与第一区域耦合的每个凸起触点与 通过再分布层与第二区域相应的凸起接触。 芯片分为第一组和第二组; 第一组堆叠在第二组上，使得第一组的每个芯片的第一区域与第二组的每个芯片的第二区域对准，并且第一组的每个芯片的第二区域与第一组的第一组对准 第二组的每个芯片的区域。 芯片通过凸块相互耦合。 芯片附接到层叠基板，第一组和第二组分别通过两个薄膜载体与触点耦合。

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