公开(公告)号：US07652383B2

公开(公告)日：2010-01-26

申请号：US11305282

申请日：2005-12-16

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC: H01L23/29

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

Abstract translation: 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US07586182B2

公开(公告)日：2009-09-08

申请号：US11289665

申请日：2005-11-28

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

Abstract translation: 本文描述的主题的方面涉及成为成品多芯片封装的部件的封装半导体管芯。 封装的半导体管芯包括管芯衬底，半导体封装和密封剂。 芯片基板包括绝缘基板和形成在绝缘基板上的电路图案。 半导体封装具有电耦合到电路图案的半导体芯片，该电路图案是已知的良好封装并且耦合到管芯衬底。 密封剂密封半导体封装。 封装的半导体管芯使用已经通过一系列封装测试的已知的良好封装。

公开(公告)号：US20090108469A1

公开(公告)日：2009-04-30

申请号：US12171035

申请日：2008-07-10

Applicant: Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

Inventor： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

Abstract translation: 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US07317247B2

公开(公告)日：2008-01-08

申请号：US11065822

申请日：2005-02-24

Applicant: Jong-Joo Lee ,  Young-Hee Song

Inventor： Jong-Joo Lee ,  Young-Hee Song

IPC: H01L23/02 ,  H01L23/34

CPC classification number: H01L23/3157 ,  H01L23/13 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15151 ,  H01L2924/15331 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor package which can be stacked to form a package stack that includes a semiconductor chip with bonding pads, a board having contact pads on its upper surface and bump pads on its lower surface, a heat spreader attached to the rear side of the semiconductor chip and covering the upper surface of the board, and external contact terminals including ground terminals and signal terminals formed on the bump pads. The contact pads of the board include ground contact pads connected with the ground terminals and signal contact pads connected with the signal terminals. The heat spreader includes indented parts to expose the signal contact pads and protruded parts to cover the ground contact pads which are exposed through holes formed on the protruded parts on the peripheral part of the heat spreader. The semiconductor package can alternatively have the heat spreader attached to the lower surface of the board.

Abstract translation: 一种半导体封装，其可堆叠形成包括具有接合焊盘的半导体芯片的封装堆叠，在其上表面上具有接触焊盘的板和在其下表面上的凸块焊盘;附接到半导体芯片的后侧的散热器 并覆盖电路板的上表面，以及包括接地端子和形成在凸块上的信号端子的外部接触端子。 板的接触垫包括与接地端子连接的接地焊盘和与信号端子连接的信号接触焊盘。 散热器包括凹陷部分，以暴露信号接触焊盘和突出部分，以覆盖通过形成在散热器的周边部分上的突出部分上的孔暴露的接地焊盘。 半导体封装也可以具有附着到板的下表面的散热器。

公开(公告)号：US20080001276A1

公开(公告)日：2008-01-03

申请号：US11790359

申请日：2007-04-25

Applicant: Jong-joo Lee ,  Sun-won Kang

Inventor： Jong-joo Lee ,  Sun-won Kang

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.

Abstract translation: 芯片堆叠可以包括堆叠在第一芯片上的第一芯片和第二芯片。 第一和第二芯片中的每一个可以包括具有活性表面和与活性表面相对的非活性表面的基底; 活动表面内部电路; 有源表面上的I / O芯片焊盘，并通过I / O缓冲器连接到内部电路; 以及通过I / O缓冲器通过电路布线连接到I / O芯片焊盘的I / O连接焊盘。 再分布的I / O芯片焊盘层可以在第一芯片的有源表面上，重新分布的I / O芯片焊盘层重新分布I / O芯片焊盘。 第一芯片和第二芯片的I / O连接焊盘可以通过电连接部分彼此电连接。

公开(公告)号：US07274097B2

公开(公告)日：2007-09-25

申请号：US11137803

申请日：2005-05-26

Applicant: Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L21/76802 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

Abstract translation: 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US20060103002A1

公开(公告)日：2006-05-18

申请号：US11261569

申请日：2005-10-31

Applicant: Mee-Hyun Ahn ,  Jong-Joo Lee ,  Yong-Jae Lee

Inventor： Mee-Hyun Ahn ,  Jong-Joo Lee ,  Yong-Jae Lee

IPC: H01L23/52

CPC classification number: H01L23/4951 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided are semiconductor devices and methods for configuring lead frames and/or device bonding pads to provide for the independent adjustment of the electrical characteristics of both fixed voltage lines, e.g., Vdd and Vss, and the signal lines, e.g., command, clock, data and address. In particular, the invention provides for adjusting the relative sizing of leads corresponding to fixed voltage lines and signal lines for increasing the relative capacitance on the fixed voltage lines to improve their stability will reducing the noise on the signal lines. The invention may be utilized with a variety of package configurations including lead-on-chip LOC configurations, more conventional quad flat pack QFP configurations in which the leads do not extend past the perimeter of the semiconductor chip or hybrid configurations in which some leads do extend past the perimeter of the semiconductor chip and across the active surface.

Abstract translation: 提供了用于配置引线框和/或器件接合焊盘以提供对两个固定电压线的电特性的独立调整的半导体器件和方法，例如V dd和V ss， / SUB>和信号线，例如命令，时钟，数据和地址。 特别地，本发明提供了调整对应于固定电压线和信号线的引线的相对尺寸以增加固定电压线上的相对电容，以提高其稳定性将降低信号线上的噪声。 本发明可以用于各种封装结构，包括片上LOC配置，更常规的四方扁平封装QFP配置，其中引线不延伸超过半导体芯片的周边或其中一些引线延伸的混合配置 通过半导体芯片的周边并穿过有源表面。

公开(公告)号：US20170278799A1

公开(公告)日：2017-09-28

申请号：US15620301

申请日：2017-06-12

Applicant: Jong-joo Lee

Inventor： Jong-joo Lee

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/538 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.

公开(公告)号：US09679853B2

公开(公告)日：2017-06-13

申请号：US13963598

申请日：2013-08-09

Applicant: Jong-joo Lee

Inventor： Jong-joo Lee

IPC: H05K7/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/538 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.

公开(公告)号：US20140252656A1

公开(公告)日：2014-09-11

申请号：US14201756

申请日：2014-03-07

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package, comprising: a substrate; a first semiconductor chip; and at least one second semiconductor chip. The first semiconductor chip and the at least one second semiconductor chip are stacked on the substrate; the first semiconductor chip is electrically connected with the substrate; and an electrical connection of each second semiconductor chip is formed through a secondary input/output buffer of the first semiconductor chip.

Abstract translation: 一种半导体封装，包括：衬底; 第一半导体芯片; 和至少一个第二半导体芯片。 第一半导体芯片和至少一个第二半导体芯片堆叠在基板上; 第一半导体芯片与衬底电连接; 并且通过第一半导体芯片的次级输入/输出缓冲器形成每个第二半导体芯片的电连接。