公开(公告)号：US09013031B2

公开(公告)日：2015-04-21

申请号：US14185394

申请日：2014-02-20

Applicant: Yunhyeok Im ,  Jichul Kim ,  Kyol Park ,  Seongho Shin

Inventor： Yunhyeok Im ,  Jichul Kim ,  Kyol Park ,  Seongho Shin

IPC: H01L23/02 ,  H01L23/36 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract translation: 半导体封装包括下封装，其包括在下封装基板上的下半导体芯片，下封装上的上封装，以及下封装和上封装之间的热界面材料。 上封装包括在上封装基板上的上半导体芯片，其包括与下半导体芯片相邻的中心部分和边缘部分。 热界面材料与下半导体芯片和上封装衬底的顶表面接触。 上封装衬底包括穿过中心部分的热扩散，以及穿过边缘部分的互连。 互连通孔与热扩散通孔间隔开。

公开(公告)号：US20150061095A1

公开(公告)日：2015-03-05

申请号：US14468361

申请日：2014-08-26

Applicant: Mi-Na Choi ,  Seran Bae ,  Yunhyeok Im

Inventor： Mi-Na Choi ,  Seran Bae ,  Yunhyeok Im

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/16 ,  H01L23/367

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2929 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and an upper semiconductor package to remove an air gap between the lower and upper semiconductor packages. Thus, heat generated from a lower semiconductor chip may be rapidly and smoothly transmitted toward the upper semiconductor package, thereby increasing or maximizing a heat exhaust effect of the PoP device.

Abstract translation: 在根据本发明构思的封装封装（PoP）器件中，各向异性导电膜设置在下半导体封装和上半导体封装之间以去除下半导体封装和上半导体封装之间的气隙。 因此，从下半导体芯片产生的热可以快速平稳地向上半导体封装传输，从而增加或最大化PoP器件的排热效果。

公开(公告)号：US20140339708A1

公开(公告)日：2014-11-20

申请号：US14243165

申请日：2014-04-02

Applicant: Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

Inventor： Eon Soo JANG ,  Kyol PARK ,  YUNHYEOK IM

IPC: H01L23/34 ,  H01L23/12 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29194 ,  H01L2224/2929 ,  H01L2224/29309 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Abstract translation: 半导体封装器件包括下封装，其包括安装在下封装基板上的下半导体芯片，设置在下封装基板上的下模塑复合层，形成在下模塑复合层中以围绕下半导体芯片的第一沟槽，以及 连接到所述第一沟槽以延伸到所述下封装的外壁的第二沟槽，所述第二沟槽形成在所述下模塑复合层中，所述上封装设置在所述下封装上。 上封装包括上封装基板和安装在上封装基板上的至少一个上半导体芯片和设置在下封装和上封装之间的传热构件。

公开(公告)号：US09391009B2

公开(公告)日：2016-07-12

申请号：US14289900

申请日：2014-05-29

Applicant: Eon Soo Jang ,  Kyol Park ,  Jongwoo Park ,  Jin-Kwon Bae ,  Yunhyeok Im ,  Jichul Kim ,  Soojae Park

Inventor： Eon Soo Jang ,  Kyol Park ,  Jongwoo Park ,  Jin-Kwon Bae ,  Yunhyeok Im ,  Jichul Kim ,  Soojae Park

IPC: H01L23/36 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/4334 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Abstract translation: 根据示例实施例，半导体封装包括下封装，下封装上的上封装并且彼此横向间隔开，下封装和上封装之间的下热排出部分，位于上封装之间的中间热排出部 并连接到下部散热部，以及上部热封装上的上部散热部，并与中间散热部连接。

公开(公告)号：US20150115467A1

公开(公告)日：2015-04-30

申请号：US14457094

申请日：2014-08-11

Applicant: Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

Inventor： Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

IPC: H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/141 ,  H05K2201/10378 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Abstract translation: 本发明的概念提供了封装封装（PoP）器件。 在PoP器件中，可以在下半导体封装和上半导体封装之间设置插入器衬底和热边界材料层，以快速排出由下半导体封装中包括的下半导体芯片产生的热。 插入器基板可以由一个或多个绝缘层，导电通孔，散热构件，保护层和各种导电图案形成。

公开(公告)号：US20140367860A1

公开(公告)日：2014-12-18

申请号：US14185394

申请日：2014-02-20

Applicant: YUNHYEOK IM ,  JICHUL KIM ,  KYOL PARK ,  SEONGHO SHIN

Inventor： YUNHYEOK IM ,  JICHUL KIM ,  KYOL PARK ,  SEONGHO SHIN

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract translation: 半导体封装包括下封装，其包括在下封装基板上的下半导体芯片，下封装上的上封装，以及下封装和上封装之间的热界面材料。 上封装包括在上封装基板上的上半导体芯片，其包括与下半导体芯片相邻的中心部分和边缘部分。 热界面材料与下半导体芯片和上封装衬底的顶表面接触。 上封装衬底包括穿过中心部分的热扩散，以及穿过边缘部分的互连。 互连通孔与热扩散通孔间隔开。

公开(公告)号：US20120280382A1

公开(公告)日：2012-11-08

申请号：US13461949

申请日：2012-05-02

Applicant: Yunhyeok IM ,  Kyol PARK ,  Taeje CHO

Inventor： Yunhyeok IM ,  Kyol PARK ,  Taeje CHO

IPC: H01L23/373

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.

Abstract translation: 提供半导体封装。 在一个实施例中，半导体封装可以包括诸如电路基板的基板，安装在电路基板上的半导体芯片，覆盖半导体芯片和电路基板并包括第一温度控制构件的模制件（或密封剂），以及 覆盖模制件的散热构件。

公开(公告)号：US20120175782A1

公开(公告)日：2012-07-12

申请号：US13347270

申请日：2012-01-10

Applicant: Yunhyeok Im ,  Tae Hong Min ,  Taeje Cho

Inventor： Yunhyeok Im ,  Tae Hong Min ,  Taeje Cho

IPC: H01L23/522

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Abstract translation: 提供半导体封装及其制造方法。 包括第一面和第二面的衬底，其中所述第一面和所述第二面彼此面对; 设置在第一面上的第一接地图案​​; 设置在所述第二面上的第二接地图案; 多个接地通孔插头，其连接第一接地图案​​和第二接地图案，其中多个接地通孔插头穿透基板; 以及插入在所述多个接地通孔插头之间的第一氧化铝膜，其中通过插头将多个接地电压施加接地电压。 半导体封装可以使用阳极氧化工艺制造。

公开(公告)号：US20120119346A1

公开(公告)日：2012-05-17

申请号：US13243996

申请日：2011-09-23

Applicant: YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

Inventor： YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/29 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00

Abstract: Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a package cap which is capable of radiating high temperatures and performs a shield function preventing transmission of electromagnetic waves into and/or out of the semiconductor package. The semiconductor package including the package cap prevents chip malfunctions and improves device reliability. The package cap is positioned to cover first and second semiconductor chips of a semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括封装帽，其能够辐射高温并执行屏蔽功能，防止电磁波进入和/或流出半导体封装。 包括封装盖的半导体封装防止芯片故障并提高器件的可靠性。 封装帽定位成覆盖半导体封装的第一和第二半导体芯片。