公开(公告)号：US07091609B2

公开(公告)日：2006-08-15

申请号：US10795502

申请日：2004-03-08

申请人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

发明人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76841 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05179 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00

摘要： Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

摘要翻译： 本发明的某些实施例涉及一种半导体器件，其具有与层间介质层具有优异相干性的焊盘部分及其制造方法。 半导体器件1000具有在层间电介质层20上形成的焊盘层30A。 垫部分30A包括润湿层32和金属布线层37。 金属布线层37包括与润湿层32接触的合金层34。 合金层34由构成润湿层32的材料和构成金属布线层37的材料形成。

公开(公告)号：US06723628B2

公开(公告)日：2004-04-20

申请号：US09817935

申请日：2001-03-27

申请人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

发明人： Kazuki Matsumoto ,  Yukio Morozumi ,  Michio Asahina

IPC分类号： H01L2144

CPC分类号： H01L24/05 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76841 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05179 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00

摘要： Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

摘要翻译： 本发明的某些实施例涉及一种半导体器件，其具有与层间介质层具有优异相干性的焊盘部分及其制造方法。 半导体器件1000具有在层间电介质层20上形成的焊盘层30A。焊盘部分30A包括润湿层32和金属布线层37.金属布线层37包括接触润湿层32的合金层34。 合金层34由构成润湿层32的材料和构成金属布线层37的材料形成。

公开(公告)号：US06559545B2

公开(公告)日：2003-05-06

申请号：US10160905

申请日：2002-06-03

申请人： Yukio Morozumi

发明人： Yukio Morozumi

IPC分类号： H01L2348

CPC分类号： H01L24/03 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48744

摘要： In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which a layer including at least a bonding pad section is formed by a damascene method, the method comprising the steps of: (a) forming an opening region 80a for the bonding pad section in an uppermost dielectric layer 22, the opening region being divided by dielectric layers 22a of a specified pattern and including a plurality of partial opening sections 81; (b) successively forming a plurality of conduction layers 820, 840 composed of different materials over the dielectric layer; and (c) removing excess portions of the plurality of conduction layers 820, 840 and the dielectric layer 22 to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section 80 in which a plurality of conduction layers 82, 84 composed of different materials are exposed in each of the partial opening sections 81 of the opening region 80a.

公开(公告)号：US06194304B1

公开(公告)日：2001-02-27

申请号：US09300378

申请日：1999-04-27

申请人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

发明人： Yukio Morozumi ,  Michio Asahina ,  Naohiro Moriya ,  Kazuki Matsumoto ,  Eiji Suzuki

IPC分类号： H01L2144

CPC分类号： H01L21/76828 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element comprises at least the following steps (a) to (c): (a) a step of forming a first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method; (b) a step of forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; and (c) a step of annealing at a temperature of 300° C. to 850° C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required for a BPSG film, and it has superior self-flattening characteristics in itself.

摘要翻译： 在包括电子元件的半导体衬底上形成层间电介质的工艺至少包括以下步骤（a）至（c）：（a）通过使包含氢的硅化合物与氢反应形成第一氧化硅层的步骤 使用化学气相沉积方法的过氧化物;（b）通过使用化学气相沉积法在包括杂质，硅化合物和至少一种选自氧的化合物和包括氧的化合物中的化合物之间反应形成多孔的第二氧化硅层的步骤 方法; 和（c）在300℃至850℃的温度下退火的步骤，以使第一和第二氧化硅层更细粒化。第一氧化硅层形成在低于该温度的温度 BPSG膜所需的，它本身具有优异的自扁平特性。

公开(公告)号：US06664644B2

公开(公告)日：2003-12-16

申请号：US10201722

申请日：2002-07-24

申请人： Yukio Morozumi

发明人： Yukio Morozumi

IPC分类号： H01L2348

CPC分类号： H01L23/3114 ,  H01L23/5387 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provide highly reliable semiconductor devices that realize further miniaturization and higher density. The invention also provides methods for manufacturing such semiconductor devices. A semiconductor device in accordance with the present invention includes a first semiconductor chip disposed face-down on a surface of a tape substrate, and a second semiconductor chip disposed face-up on a rear surface of the first semiconductor chip. The semiconductor device is equipped with a wiring pattern formed on a surface of the tape substrate, solder bumps formed on a rear surface of the tape substrate, solder balls of the first semiconductor chip connected to the wiring pattern, bonding pads formed on a surface of the second semiconductor chip, bonding wires that connect the bonding pads and the wiring pattern, and a resin that seals the surface of the tape substrate, the bonding wires, and the first and second semiconductor chips.

公开(公告)号：US06498090B2

公开(公告)日：2002-12-24

申请号：US09775474

申请日：2001-02-03

申请人： Yukio Morozumi

发明人： Yukio Morozumi

IPC分类号： H01L214763

CPC分类号： H01L23/53238 ,  H01L21/76877 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13091 ,  Y10T428/2495 ,  H01L2924/00

摘要： In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method. The method includes the following steps of: (a) forming an uppermost dielectric layer 22 in which an uppermost wiring layer is formed; (b) forming a wiring groove for the wiring layer having a specified pattern and an opening section for bonding pad section in the uppermost dielectric layer 22; (c) forming a first conduction layer for the wiring layer; (d) forming a second conduction layer over the first conduction layer, the second conduction layer composed of a different material from a material of the first conduction layer; and (e) planarizing the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer 62 composed of the first conduction layer in the wiring groove and a base conduction layer 82 composed of the first conduction layer and an exposed conduction layer 84 composed of the second conduction layer in the opening section for bonding pad section.

摘要翻译： 在通过镶嵌方法形成布线层的半导体器件的制造方法中，某些实施例涉及一种制造方法和半导体器件，其中可以通过简单的方法形成具有多层结构的焊盘部分 而不增加处理步骤的数量。 一个实施例包括一种制造半导体器件的方法，其中至少最上层的布线层通过镶嵌法形成。 该方法包括以下步骤：（a）形成其中形成最上层的布线层的最上层的电介质层22; （b）在最上层电介质层22中形成用于具有指定图案的布线层的布线槽和用于焊盘区段的开口部分; （c）形成布线层的第一导电层; （d）在所述第一导电层上形成第二导电层，所述第二导电层由与所述第一导电层的材料不同的材料构成; 和（e）平面化第二导电层，第一导电层和电介质层，从而形成由布线槽中的第一导电层构成的布线层62和由第一导电层构成的基极导电层82和 在用于接合焊盘部的开口部中由第二导电层构成的暴露的导电层84。

公开(公告)号：US5514624A

公开(公告)日：1996-05-07

申请号：US93377

申请日：1993-07-19

申请人： Yukio Morozumi

发明人： Yukio Morozumi

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/31055 ,  H01L21/76819

摘要： A method of manufacturing an interlayer dielectric for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.

摘要翻译： 制造具有多个导电层的微电子器件的层间电介质的方法提供了用于沉积后续层的平坦化表面，并且通过将旋涂玻璃厚度限制在约0.4μm或更小而进一步防止旋涂玻璃的开裂。 通过使Si（OC 2 H 5）4和O 2在大约9托下在370℃至400℃之间使第一导电层形成第一介电层，并且通过在第一介电层上形成第二介电层 与用于形成第一介电层的方法不同的方法。 在蚀刻回第二介电层之后，形成旋涂玻璃层。 旋转玻璃层被回蚀以提供平面表面，并且在旋涂玻璃层上形成第三介电层。 所得到的表面准备好接触孔形成，沉积和后续导电和绝缘层的图案化。

公开(公告)号：US5376435A

公开(公告)日：1994-12-27

申请号：US92834

申请日：1993-07-16

申请人： Yukio Morozumi

发明人： Yukio Morozumi

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  B32B9/00

CPC分类号： H01L21/31055 ,  H01L21/76819 ,  Y10T428/24917 ,  Y10T428/24926

摘要： An interlayer dielectric structure for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric-layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.

摘要翻译： 具有多个导电层的微电子器件的层间电介质结构提供了用于沉积后续层的平坦化表面，并且通过将旋涂玻璃厚度限制在约0.4μm或更小而进一步防止旋涂玻璃的开裂。 通过使Si（OC 2 H 5）4和O 2在大约9托下在370℃至400℃之间使第一导电层形成第一介电层，并且通过在第一介电层上形成第二介电层 与用于形成第一介电层的方法不同的方法。 在蚀刻回第二介电层之后，形成旋涂玻璃层。 旋转玻璃层被回蚀以提供平面表面，并且在旋涂玻璃层上形成第三介电层。 所得到的表面准备好接触孔形成，沉积和后续导电和绝缘层的图案化。

公开(公告)号：US3988181A

公开(公告)日：1976-10-26

申请号：US365371

申请日：1973-05-30

申请人： Fukashi Imai ,  Yukio Morozumi

发明人： Fukashi Imai ,  Yukio Morozumi

IPC分类号： H01L27/04 ,  H01L21/00 ,  H01L21/02 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/822 ,  H01L23/29 ,  H01L7/34

CPC分类号： H01L28/20 ,  H01L21/00 ,  H01L21/32155 ,  H01L23/291 ,  H01L2924/0002 ,  Y10S148/118 ,  Y10S148/122

摘要： An improved wafer type semiconductor may be fabricated by depositing an insulating film layer of predetermined thickness on a semiconductor substrate, preferably of silicon, depositing a substantially pure polycrystalline silicon layer of predetermined thickness on the insulating film layer, and thereafter depositing a doped oxide film layer of predetermined thickness on the substantially pure polycrystalline silicon layer, and effecting diffusion of the dopant into the pure polycrystalline silicon layer whereby a semiconductor wafer with a resistance of several meg-ohms.cm is provided.

摘要翻译： 改进的晶片型半导体可以通过在半导体衬底（优选硅）上沉积预定厚度的绝缘膜层来在绝缘膜层上沉积预定厚度的基本上纯的多晶硅层，然后沉积掺杂的氧化物膜层 在基本上纯的多晶硅层上具有预定厚度，并且使掺杂剂扩散到纯多晶硅层中，从而提供具有几兆欧姆·厘米电阻的半导体晶片。