公开(公告)号：US08993419B1

公开(公告)日：2015-03-31

申请号：US14045467

申请日：2013-10-03

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/302 ,  H01L29/66

CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US12297559B2

公开(公告)日：2025-05-13

申请号：US17961463

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Hua Chung ,  Flora Fong-Song Chang

IPC: C30B25/18 ,  C23C16/02 ,  C23C16/24 ,  C23C16/54 ,  C23C16/56 ,  C30B29/06 ,  C30B33/12 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687

Abstract: Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

公开(公告)号：US20230227968A1

公开(公告)日：2023-07-20

申请号：US18190246

申请日：2023-03-27

Applicant: Applied Materials, Inc.

Inventor： Feng Q. Liu ,  Hua Chung ,  Schubert Chu ,  Mei Chang ,  Jeffrey W. Anthis ,  David Thompson

IPC: C23C16/42 ,  C23C16/513 ,  C23C16/455 ,  C23C16/52 ,  C23C16/507 ,  C23C16/14

CPC classification number: C23C16/42 ,  C23C16/513 ,  C23C16/45536 ,  C23C16/52 ,  C23C16/507 ,  C23C16/45542 ,  C23C16/14

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

公开(公告)号：US11649559B2

公开(公告)日：2023-05-16

申请号：US16266646

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Chun Yan ,  Hua Chung ,  Schubert S. Chu

IPC: C30B25/16 ,  C30B25/08 ,  C30B25/00 ,  C30B33/00 ,  C23C16/44 ,  C23C16/30 ,  C23C16/48 ,  C23C16/56 ,  C30B25/10 ,  C30B25/12 ,  C30B25/14 ,  C30B29/40 ,  H01L21/67 ,  C30B35/00 ,  H01L21/225 ,  H01L21/30 ,  C30B29/06

CPC classification number: C30B25/08 ,  C23C16/301 ,  C23C16/4405 ,  C23C16/481 ,  C23C16/56 ,  C30B25/00 ,  C30B25/105 ,  C30B25/12 ,  C30B25/14 ,  C30B25/165 ,  C30B29/40 ,  C30B33/00 ,  C30B35/00 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67253 ,  C30B29/06 ,  H01L21/2252 ,  H01L21/30 ,  H01L21/67201

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

公开(公告)号：US10332739B2

公开(公告)日：2019-06-25

申请号：US15417466

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  B08B7/00 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67 ,  C23C16/44 ,  C23C16/56

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.

公开(公告)号：US10312096B2

公开(公告)日：2019-06-04

申请号：US15832571

申请日：2017-12-05

Applicant: Applied Materials, Inc.

Inventor： Hua Chung ,  Matthias Bauer ,  Schubert S. Chu ,  Satheesh Kuppurao

IPC: H01L21/285 ,  H01L29/167 ,  H01L29/45 ,  H01L21/3205 ,  H01L21/324 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

Abstract: The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.

公开(公告)号：US10269647B2

公开(公告)日：2019-04-23

申请号：US15811188

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Schubert S. Chu ,  Xinyu Bao ,  Regina Germanie Freed ,  Hua Chung

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

公开(公告)号：US10224421B2

公开(公告)日：2019-03-05

申请号：US15933072

申请日：2018-03-22

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Xinyu Bao ,  Chun Yan ,  Hua Chung ,  Schubert S. Chu ,  Satheesh Kuppurao

IPC: H01L29/26 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8252 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/67

Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.

公开(公告)号：US20180158682A1

公开(公告)日：2018-06-07

申请号：US15882939

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

公开(公告)号：US09881790B2

公开(公告)日：2018-01-30

申请号：US15091332

申请日：2016-04-05

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.