公开(公告)号：US20180337130A1

公开(公告)日：2018-11-22

申请号：US15596956

申请日：2017-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Shih-Yu WANG ,  Chang Chi LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

公开(公告)号：US20160300782A1

公开(公告)日：2016-10-13

申请号：US14685529

申请日：2015-04-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Chin-Li KAO ,  Kuo-Hua CHEN ,  Ming-Hung CHEN ,  Dao-Long CHEN

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49548 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

Abstract translation: 本公开涉及一种半导体封装结构及其制造方法。 半导体封装结构包括引线框和半导体管芯。 引线框架包括主体部分和突出部分。 半导体管芯结合到主要部分的第一表面。 突出部分从主体部分的第二表面突出。 突起部分的位置对应于半导体管芯的位置。

公开(公告)号：US20160240481A1

公开(公告)日：2016-08-18

申请号：US14624331

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Ching CHEN ,  Chin-Li KAO ,  Hung-Jen CHANG ,  Tang-Yuan CHEN ,  Wei-Hong LAI

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K3/205 ,  H05K2201/10378

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

Abstract translation: 这里描述了用于翘曲控制的插入式衬底设计，包括所述插入器衬底的半导体结构及其制造工艺。 插入器基板限定空腔并且还包括加强结构，其中加强结构用于控制半导体封装结构的翘曲。

公开(公告)号：US20240334586A1

公开(公告)日：2024-10-03

申请号：US18129768

申请日：2023-03-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Hung-Hsien HUANG ,  Chin-Li KAO

IPC: H05K1/02 ,  H05K3/10 ,  H05K5/00

CPC classification number: H05K1/0201 ,  H05K3/103 ,  H05K5/0091

Abstract: A package structure is provided. The package structure includes an electronic component, a heat dissipating element, a thermal interfacing unit, and a confining structure. The electronic component has an upper surface. The heat dissipating element is over the upper surface of the electronic component. The thermal interfacing unit is between the upper surface of the electronic component and the heat dissipating element. The thermal interfacing unit includes a thermal interfacing material (TIM). The TIM is attached to the confining structure by capillary force.

公开(公告)号：US20220230946A1

公开(公告)日：2022-07-21

申请号：US17151062

申请日：2021-01-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei SHIH ,  Sheng-Wen YANG ,  Chung-Hung LAI ,  Chin-Li KAO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31

Abstract: A substrate structure and a semiconductor package structure are provided. The substrate structure includes a first dielectric layer, a pad and a conductive structure. The first dielectric layer has a first surface and a second surface opposite to the first surface. The pad is adjacent to the first surface and at least partially embedded in the first dielectric layer. The first dielectric layer has an opening exposing the pad, and a width of the opening is less than a width of the pad. The conductive structure is disposed on the pad and composed of a first portion outside the opening of the first dielectric layer and a second portion embedded in the opening of the first dielectric layer. The first portion has an aspect ratio exceeding 1.375.

公开(公告)号：US20210265231A1

公开(公告)日：2021-08-26

申请号：US16799751

申请日：2020-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Hung-Jung TU ,  Chang Chi LEE ,  Chin-Li KAO

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US20170263589A1

公开(公告)日：2017-09-14

申请号：US15416907

申请日：2017-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chang Chi LEE ,  Chin-Li KAO ,  Dao-Long CHEN ,  Ta-Chien CHENG

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3672 ,  H01L24/33 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

公开(公告)号：US20140332957A1

公开(公告)日：2014-11-13

申请号：US14274289

申请日：2014-05-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li KAO ,  Chang-Chi LEE ,  Yi-Shao LAI

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract translation: 本发明涉及半导体封装及其制造方法。半导体封装包括半导体元件，其包括主体，多个导电通孔和至少一个填充物。 导电通孔穿过主体。 填料位于主体中，填料的热膨胀系数（CTE）与主体和导电通孔的热膨胀系数不同。 因此，可以调整整个半导体元件的CTE，以便减少翘曲。

公开(公告)号：US20240413115A1

公开(公告)日：2024-12-12

申请号：US18207090

申请日：2023-06-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ling YEH ,  Yuan-Feng CHIANG ,  Chung-Hung LAI ,  Chin-Li KAO

IPC: H01L23/00 ,  H01L23/31

Abstract: A package structure is provided. The package structure includes an electronic component, an encapsulant, a first conductive pillar, a first dielectric layer. The electronic component has an active surface. The encapsulant encapsulates the electronic component and exposes the active surface of the electronic component. The first conductive pillar is over the active surface of the electronic component, wherein an upper surface of the first conductive pillar includes a concave portion. The first dielectric layer is over the encapsulant and the active surface of the electronic component, wherein the first dielectric layer defines an opening exposing the concave portion of the first conductive pillar.

公开(公告)号：US20210335715A1

公开(公告)日：2021-10-28

申请号：US16858269

申请日：2020-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li KAO

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.