公开(公告)号：US20170168383A1

公开(公告)日：2017-06-15

申请号：US15444864

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ralf Hofmann ,  Kevin Moraes

IPC: G03F1/22 ,  C23C14/16 ,  C23C14/35 ,  C23C14/54 ,  G03F7/20 ,  C23C14/22

CPC classification number: G03F1/22 ,  C23C14/16 ,  C23C14/165 ,  C23C14/221 ,  C23C14/35 ,  C23C14/352 ,  C23C14/541 ,  G03F7/70958

Abstract: An integrated extreme ultraviolet blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a deposition system for depositing a multi-layer stack without removing the substrate from the vacuum; and a treatment system for treating a layer on the multi-layer stack to be deposited as an amorphous metallic layer. A physical vapor deposition chamber for manufacturing an extreme ultraviolet mask blank includes: a target, comprising molybdenum alloyed with boron. An extreme ultraviolet lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for placing an extreme ultraviolet mask blank with a multi-layer stack having an amorphous metallic layer; and a wafer stage for placing a wafer. An extreme ultraviolet blank includes: a substrate; a multi-layer stack having an amorphous metallic layer; and capping layers over the multi-layer stack.

公开(公告)号：US11959167B2

公开(公告)日：2024-04-16

申请号：US17834633

申请日：2022-06-07

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho Yu ,  Kevin Moraes ,  Seshadri Ganguli ,  Hua Chung ,  See-Eng Phan

IPC: C23C16/16 ,  C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768

CPC classification number: C23C16/16 ,  C23C16/0218 ,  C23C16/0245 ,  C23C16/18 ,  C23C16/4554 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US10707122B2

公开(公告)日：2020-07-07

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/32 ,  H01L21/02 ,  H01L21/3105

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20180144973A1

公开(公告)日：2018-05-24

申请号：US15800784

申请日：2017-11-01

Applicant: Applied Materials, Inc.

Inventor： Weifeng Ye ,  Jiang Lu ,  Feng Chen ,  Zhiyuan Wu ,  Kai Wu ,  Vikash Banthia ,  He Ren ,  Sang Ho Yu ,  Mei Chang ,  Feiyue Ma ,  Yu Lei ,  Keyvan Kashefizadeh ,  Kevin Moraes ,  Paul F. Ma ,  Hua Ai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7685 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 Å to about 60 Å.

公开(公告)号：US08895450B2

公开(公告)日：2014-11-25

申请号：US14054477

申请日：2013-10-15

Applicant: Applied Materials, Inc.

Inventor： Yong Cao ,  Xianmin Tang ,  Srinivas Gandikota ,  Wei D. Wang ,  Zhendong Liu ,  Kevin Moraes ,  Muhammad M. Rasheed ,  Thanh X. Nguyen ,  Ananthkrishna Jupudi

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/28 ,  C23C14/35 ,  H01L21/285 ,  C23C14/34 ,  H01L29/49 ,  C23C14/16 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/28079 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/28088 ,  H01L21/2855 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

Abstract translation: 本文所述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。