公开(公告)号：US5147821A

公开(公告)日：1992-09-15

申请号：US786205

申请日：1991-10-31

申请人： Michael B. McShane ,  James J. Casto ,  Bennett A. Joiner

发明人： Michael B. McShane ,  James J. Casto ,  Bennett A. Joiner

IPC分类号： H01L21/56 ,  H01L23/433

CPC分类号： H01L21/565 ,  H01L23/4334 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815

摘要： A method for making a semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounting surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads are encapsulated in a package body. Also incorporated into the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

摘要翻译： 提供一种制造具有散热器的半导体器件的方法，其中通过散热器的开口能够将真空源施加到半导体管芯安装表面。 在一种形式中，半导体管芯附接到引线框架的安装表面。 引线框架还具有电耦合到半导体管芯的多个引线。 半导体管芯和引线的部分被封装在封装主体中。 还包括在包装体内的是散热器。 散热器具有延伸穿过散热器并且暴露引线框的安装表面的一部分的开口。 开口用于在形成包装体期间向安装表面施加真空，使得安装表面和散热器保持紧密。 接近性提供了从半导体管芯到环境的良好的热传导路径，从而增强了器件的散热特性。

公开(公告)号：US5105259A

公开(公告)日：1992-04-14

申请号：US589465

申请日：1990-09-28

申请人： Michael B. McShane ,  James J. Casto ,  Bennett A. Joiner

发明人： Michael B. McShane ,  James J. Casto ,  Bennett A. Joiner

IPC分类号： H01L21/56 ,  H01L23/433

CPC分类号： H01L21/565 ,  H01L23/4334 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1532 ,  H01L2924/181

摘要： A semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounted surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads encapsulated in a package body. Also incorporated in the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

摘要翻译： 提供了具有散热器的半导体器件，其中通过散热器的开口能够将真空源施加到半导体管芯安装表面。 在一种形式中，半导体管芯附接到引线框架的安装表面。 引线框架还具有电耦合到半导体管芯的多个引线。 半导体管芯和封装在封装主体中的引线部分。 还包括在包装体中的是散热器。 散热器具有延伸穿过散热器并且暴露引线框的安装表面的一部分的开口。 开口用于在形成包装体期间向安装表面施加真空，使得安装表面和散热器保持紧密。 接近性提供了从半导体管芯到环境的良好的热传导路径，从而增强了器件的散热特性。

公开(公告)号：US20130088255A1

公开(公告)日：2013-04-11

申请号：US13268681

申请日：2011-10-07

申请人： PERRY H. PELLEY ,  Kevin J. Hess ,  Michael B. McShane

发明人： PERRY H. PELLEY ,  Kevin J. Hess ,  Michael B. McShane

IPC分类号： G01R31/26 ,  H01L23/48 ,  H01L23/544

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L22/32 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06596

摘要： A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

摘要翻译： 叠层半导体器件包括第一和第二半导体器件。 第一和第二装置中的每一个的第一主表面包括有源电路直接面对彼此。 每个装置的第一主表面包括在至少一个边缘上的斜边缘和延伸到斜边上的探针垫。 第一开口位于堆叠半导体器件的垂直侧上的第一和第二器件的斜边之间。

公开(公告)号：US07777330B2

公开(公告)日：2010-08-17

申请号：US12026325

申请日：2008-02-05

申请人： Perry H. Pelley ,  Michael B. McShane

发明人： Perry H. Pelley ,  Michael B. McShane

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

摘要翻译： 处理器/高速缓存组件具有耦合到高速缓冲存储器模块的处理器管芯。 处理器管芯具有排列成阵列的多个处理器单元。 在处理器单元上存在多个处理器组的接触焊盘，每个处理器单元设置一个处理器组。 类似地，高速缓存管芯具有排列成阵列的多个高速缓存单元。 高速缓存芯片上存在多个高速缓存集合的接触焊盘，每个高速缓存单元具有一个高速缓存集。 每个缓存集与一个相应的处理器集接触。

公开(公告)号：US20100117242A1

公开(公告)日：2010-05-13

申请号：US12267728

申请日：2008-11-10

申请人： Gary L. Miller ,  Michael B. McShane

发明人： Gary L. Miller ,  Michael B. McShane

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/17 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device includes an intermediate substrate having a first surface and a second surface, a first die attached to the first surface of the intermediate substrate. The first die has a first active surface, and the first active surface faces the intermediate substrate. A second die is attached to the second surface of the intermediate substrate, has a second active surface, faces the intermediate substrate, and is coupled to the first die through an electrically conductive material in the intermediate substrate. An organic material encapsulates at least an edge of the intermediate substrate. There is also a method of forming the semiconductor device.

摘要翻译： 半导体器件包括具有第一表面和第二表面的中间衬底，附接到中间衬底的第一表面的第一管芯。 第一模具具有第一活性表面，并且第一活性表面面向中间基材。 第二管芯附接到中间衬底的第二表面，具有第二有源表面，面向中间衬底，并通过中间衬底中的导电材料耦合到第一管芯。 有机材料至少包封中间基板的边缘。 还有一种形成半导体器件的方法。

公开(公告)号：US5311057A

公开(公告)日：1994-05-10

申请号：US982549

申请日：1992-11-27

申请人： Michael B. McShane

发明人： Michael B. McShane

IPC分类号： H01L23/495 ,  H01L23/02 ,  H01L23/49 ,  H01L23/522 ,  H01L29/44

CPC分类号： H01L23/49589 ,  H01L23/4951 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107

摘要： A lead-on-chip (LOC) semiconductor device (10) has an integral decoupling capacitor in the form of a capacitor tape (20) attached to an active surface (14) of a semiconductor die (12). The capacitor tape includes two adhesive layers (22 and 24) to bond the die to the capacitor tape and to a plurality of leads (18). The tape also includes two conductive layers (26 and 28), made for instance of copper foil, which serve as the two electrodes of the capacitor. The electrodes are separated by a dielectric layer (30) which in one embodiment comprises barium-titanate (BaTiO.sub.3). The electrodes of the capacitor are electrically coupled to appropriate power and ground leads of the device by bonding wires (36 and 40) and to appropriate bonding pads (16) also by bonding wires (38 and 42). The bonding wires can be configured using any of three available wiring options. The present invention can also be implemented in a chip-on-lead (COL) device.

摘要翻译： 片上芯片（LOC）半导体器件（10）具有以与半导体管芯（12）的有源表面（14）连接的电容器带（20）形式的整体去耦电容器。 电容带包括两个粘合层（22和24），用于将管芯连接到电容器带和多个引线（18）。 该带还包括用作例如电容器的两个电极的铜箔制成的两个导电层（26和28）。 电极由电介质层（30）分开，在一个实施例中电介质层包括钛酸钡（BaTiO 3）。 电容器的电极通过接合线（36和40）以及也通过接合线（38和42）与适当的接合焊盘（16）电耦合到器件的适当的电源和接地引线。 可以使用三种可用接线选项中的任何一种来配置接合线。 本发明也可以在芯片引线（COL）器件中实现。

公开(公告)号：US5294827A

公开(公告)日：1994-03-15

申请号：US991548

申请日：1992-12-14

申请人： Michael B. McShane

发明人： Michael B. McShane

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/49558 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165

摘要： A thin semiconductor device (50) can be cost effectively manufactured using conventional wire bonding technology and stamped leadframes. A flagless leadframe (12) is utilized in one embodiment. A support tape (14) having a die support surface (20) is attached transversely to a plurality of leads (18) of the leadframe. A semiconductor die (16) is attached on its active surface to the die support surface such that the active surface is coplanar with the leadframe. Low loop wire bonds (24) electrically connect the die to the leadframe. A resin encapsulant package body (52) is molded around the active surface of the die, the wire bonds, and a portion of the leads. An inactive surface of the die is exposed for enhanced thermal dissipation in addition to enabling a thin package body. External lead configuration of the semiconductor device is not limited.

摘要翻译： 可以使用传统的引线键合技术和冲压的引线框架成本有效地制造薄的半导体器件（50）。 在一个实施例中使用无标志引线框架（12）。 具有模具支撑表面（20）的支撑带（14）横向于引导框架的多个引线（18）安装。 半导体管芯（16）在其有源表面上连接到管芯支撑表面，使得有源表面与引线框架共面。 低环线接合（24）将管芯与引线框电连接。 在模具的有效表面周围模制树脂密封剂封装体（52），引线键合和引线的一部分。 暴露裸片的非活性表面，以增强散热性，同时还能实现薄封装体。 半导体器件的外部引线配置不受限制。

公开(公告)号：US5247423A

公开(公告)日：1993-09-21

申请号：US887963

申请日：1992-05-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14

CPC分类号： H01L23/4985 ,  H01L23/3121 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/144 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025

摘要： A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

公开(公告)号：US5049526A

公开(公告)日：1991-09-17

申请号：US362644

申请日：1989-06-07

申请人： Michael B. McShane ,  Paul T. Lin

发明人： Michael B. McShane ,  Paul T. Lin

IPC分类号： B29C45/14 ,  H01L21/56

CPC分类号： B29C45/14655 ,  H01L21/565 ,  H01L2224/48247 ,  Y10T29/49121

摘要： A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area. A semiconductor device die is secured to the lead frame and the lead frame with the die attached is aligned within the encapsulation mold to place the semiconductor device die and the inner ends of the leads within the cavity defined by the inserts. The outer ends of the leads extend through the second chamber. Plastic material is then injected into the mold to form the device package body about the semiconductor device die. The package body is shaped by the cavity and the inserts and the carrier ring is shaped by the second chamber.

公开(公告)号：US5012386A

公开(公告)日：1991-04-30

申请号：US428089

申请日：1989-10-27

申请人： Michael B. McShane ,  Paul Lin

发明人： Michael B. McShane ,  Paul Lin

IPC分类号： H01L23/36 ,  H01L21/60 ,  H01L23/057 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L24/49 ,  H01L23/057 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/32188 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195

摘要： A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed. Since the IC chip or other component is directly mounted on the insert, waste heat generated by the chip may be directly channeled outside the package through the insert which effectively forms one wall of the package. The exposed leads may be formed into the desired configuration, including shapes suitable for surface mount technology. The use of a multiple layer substate permits the inclusion of ground and power planes for high performance circuits, such as emitter coupled logic (ECL) gate arrays, within the package itself.

摘要翻译： 用于包含高性能电子元件的封装，例如高速集成电路（IC）。 该封装件具有其中具有空腔的多层衬底。 引线可以放置在衬底中的孔内并焊接或以其他方式电连接到衬底中的导电图案或层。 导热插入件附接到子状态的一侧。 插入件具有突出通过基板中的空腔的基座。 然后，诸如IC的电子部件可以安装在基座上并电连接到衬底的一个层上的导电金属图案。 然后可以用电介质材料涂覆该组件以形成封装体，留下引线的远端和插入件的背面露出。 由于IC芯片或其他部件直接安装在插入件上，所以由芯片产生的废热可以通过插入件直接引导到封装外部，从而有效地形成封装的一个壁。 暴露的引线可以形成为期望的构造，包括适合于表面贴装技术的形状。 使用多层子状态允许在封装本身内包含用于高性能电路（例如发射极耦合逻辑（ECL）门阵列）的接地和电源平面。