公开(公告)号：US5229257A

公开(公告)日：1993-07-20

申请号：US516415

申请日：1990-04-30

申请人： John E. Cronin ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Jung H. Yoon

发明人： John E. Cronin ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Jung H. Yoon

IPC分类号： C08G73/10 ,  G03F7/038 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46

CPC分类号： H01L21/76828 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L23/5226 ,  H05K3/0023 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K2201/0154 ,  H05K3/045 ,  H05K3/107 ,  H05K3/465

摘要： Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

公开(公告)号：US5194928A

公开(公告)日：1993-03-16

申请号：US842307

申请日：1992-02-26

申请人： John E. Cronin ,  Paul A. Farrar, Sr. ,  Harold G. Linde ,  Rosemary A. Previti-Kelly

发明人： John E. Cronin ,  Paul A. Farrar, Sr. ,  Harold G. Linde ,  Rosemary A. Previti-Kelly

IPC分类号： C08G73/10 ,  C09D4/00 ,  G03F7/075 ,  G03F7/09 ,  H01L21/312

CPC分类号： H01L21/3121 ,  C08G73/106 ,  C09D4/00 ,  G03F7/0757 ,  G03F7/094 ,  H01L21/312 ,  Y10S438/958

摘要： Disclosed is a process for passivating a metal surface in a metal/polyimide structure, such as a polyimide layer on a semiconductor substrate containing a pattern of metallization. The process involves the formation of an intermediate layer of a silsesquioxane polymer between the polyimide layer and the substrate. The silsesquioxane layer passivates the metal, to inhibit interaction between the metal surface and the polyimide precursor material used in forming the polyimide, to provide a moisture-resistant and oxidation-resistant interface.

摘要翻译： 公开了一种在包含金属化图案的半导体衬底上的金属/聚酰亚胺结构如聚酰亚胺层中钝化金属表面的方法。 该方法涉及在聚酰亚胺层和基底之间形成倍半硅氧烷聚合物的中间层。 倍半硅氧烷层钝化金属，以抑制金属表面与形成聚酰亚胺所用的聚酰亚胺前体材料之间的相互作用，以提供耐湿和抗氧化的界面。

公开(公告)号：US5136124A

公开(公告)日：1992-08-04

申请号：US585256

申请日：1990-09-19

申请人： John E. Cronin ,  Carter W. Kaanta ,  Michael A. Leach

发明人： John E. Cronin ,  Carter W. Kaanta ,  Michael A. Leach

IPC分类号： H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/46

CPC分类号： H01L21/76808 ,  H01L21/32053 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/7688 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0017 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4644

摘要： A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers of insulating material are provided wherein the first and third layers are separated by the second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot between the first and third layers of insulating material. Also openings are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.

摘要翻译： 提供了用于在两层绝缘材料之间形成导电线的方法以及将绝缘材料的两层连接到相对表面的方法。 在该方法中，提供了绝缘材料的第一层，第二层和第三层，其中第一层和第三层由第二层绝缘材料隔开，蚀刻速率与第一层和第三层不同。 暴露所有三层的边缘部分，并且选择性地蚀刻第二材料的绝缘层以去除露出的边缘部分，并在第一和第三绝缘材料层之间提供槽。 在第一和第三绝缘材料层中的开口均设置有与槽连通并分别延伸穿过第一和第三绝缘材料的层。 此后，诸如钨的导电材料沉积在槽和开口中以及堆叠的绝缘材料的表面上。 最后，从第一和第三层的绝缘材料的表面去除多余的钨，留下夹在材料的第一和第三绝缘层之间的导线; 在形成的开口中也保留有金属，从而形成从线形延伸到形成的绝缘材料夹层的相对表面的导电柱。

公开(公告)号：US6139661A

公开(公告)日：2000-10-31

申请号：US175916

申请日：1998-10-20

申请人： John E. Cronin ,  Joseph D. Poole ,  Michael C. Weller

发明人： John E. Cronin ,  Joseph D. Poole ,  Michael C. Weller

IPC分类号： C09J5/00 ,  H05K3/32 ,  B32B31/28

CPC分类号： H05K3/321 ,  C09J5/00 ,  H05K2201/10689 ,  H05K2203/0557 ,  H05K2203/1476 ,  H05K2203/162 ,  H05K2203/176 ,  Y10T29/4913 ,  Y10T29/49147

摘要： A method for temporarily attaching an electrical component to a pad, testing the component, removing and replacing the component if necessary, and making a final attachment of the component to the pad. The method provides for attachment and removal of components, to and from pads located on the substrate of a printed circuit board, wherein the method enables components to be easily removed prior to final assembly without damaging the circuit board or components mounted thereon. The method utilizes a layer of conductive, radiation-curable adhesive placed between the component's lead and the pad. Radiation is then directed through a mask onto a portion of the adhesive layer, which cures the portion while leaving a remaining area of the adhesive layer uncured. Because the portion of the adhesive layer that receives the radiation, and is consequently cured by the radiation, is only a limited portion of the whole adhesive layer, the component may be easily removed from the pad by applying a small mechanical force. Following such removal, the component or a replacement thereof may be attached to the remaining area. The final stage of the method cures the remaining area of uncured adhesive by exposing the remaining area to radiation.

摘要翻译： 一种用于将电气部件临时附接到焊盘，测试部件，如果需要移除和更换部件的方法，以及将部件最终附接到焊盘。 该方法提供了附接和去除位于印刷电路板的基板上的焊盘的部件，其中该方法使得能够在最终组装之前容易地移除部件，而不会损坏安装在其上的电路板或部件。 该方法利用放置在部件的引线和焊盘之间的导电的可辐射固化的粘合剂层。 然后将辐射通过掩模引导到粘合剂层的一部分上，其固化该部分，同时留下未固化的粘合剂层的剩余区域。 由于接收辐射并因此被辐射固化的粘合剂层的部分仅仅是整个粘合剂层的有限部分，所以通过施加小的机械力可以容易地将该部件从焊盘移除。 在这种移除之后，组件或其替换可以附接到剩余区域。 该方法的最后阶段通过将剩余区域暴露于辐射来固化未固化的粘合剂的剩余面积。

公开(公告)号：US6037661A

公开(公告)日：2000-03-14

申请号：US771598

申请日：1996-12-20

申请人： Anthony M. Palagonia ,  John E. Cronin

发明人： Anthony M. Palagonia ,  John E. Cronin

IPC分类号： H01L23/24 ,  H01L23/495 ,  H01L31/0232

CPC分类号： H01L23/49575 ,  H01L23/24 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14

摘要： A semiconductor device which includes a first semiconductor chip mounted on top of a lead frame which is molded within a plastic body. During the molding process a cavity is formed on the bottom of the lead frame. After testing or burn-in of the first chip a second semiconductor chip is mounted and electrically connected to the lead frame. The second chip may then be sealed within the cavity to form a multichip module.

摘要翻译： 一种半导体器件，包括安装在引线框架的顶部上的第一半导体芯片，所述引线框架模制在塑料体内。 在模制过程中，在引线框架的底部形成空腔。 在第一芯片的测试或老化之后，安装第二个半导体芯片并电连接到引线框架。 然后可以将第二芯片密封在空腔内以形成多芯片模块。

公开(公告)号：US5872025A

公开(公告)日：1999-02-16

申请号：US815452

申请日：1997-03-11

申请人： John E. Cronin ,  Anthony Palagonia ,  Bernadette A. Pierson ,  Dennis A. Schmidt

发明人： John E. Cronin ,  Anthony Palagonia ,  Bernadette A. Pierson ,  Dennis A. Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L21/283 ,  H01L21/027 ,  H01L21/18 ,  H01L21/31

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.

摘要翻译： 堆叠的三维器件可以通过堆叠晶片作为堆叠单个器件的替代物来制备。 芯片区域形成在几个晶片上，每个芯片区域被诸如绝缘体填充的沟槽之类的分离区域包围。 然后将晶片与芯片区域对准地堆叠。 可以利用晶片周边的切口区域来调整晶片对准。 然后通过层压将晶片连接在一起。 在堆叠晶片堆叠之后，通过蚀刻，切割或其它工艺来分离芯片堆叠，其在芯片分离区域将堆叠的芯片器件与堆叠晶片分开。 该过程允许同时制造几个堆叠的芯片器件。

公开(公告)号：US5795830A

公开(公告)日：1998-08-18

申请号：US686481

申请日：1996-07-26

申请人： John E. Cronin ,  Carter W. Kaanta

发明人： John E. Cronin ,  Carter W. Kaanta

IPC分类号： H01L21/033 ,  H01L21/3065 ,  C03C25/06

CPC分类号： H01L21/0338 ,  H01L21/0334

摘要： A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.

摘要翻译： 公开了一种在其间形成次光刻元件和间隔的方法，其中间距可以通过连续可调的线和空间尺寸减小，并且由该方法得到的结构。 在基板上形成多个间隔开的可转换构件。 然后将每个构件的一部分转换，从而减小构件的未转换部分的尺寸，同时增加构件加上其转换层的宽度。 然后将保形层材料沉积在转换的部件上，然后定向蚀刻保形层。 然后移除该成员的未转换部分。 可以通过改变成员的转换层和保形层中的一个或两个来连续地调整线和空间尺寸。

公开(公告)号：US5549511A

公开(公告)日：1996-08-27

申请号：US349848

申请日：1994-12-06

申请人： John E. Cronin ,  Matthew J. Rutten

发明人： John E. Cronin ,  Matthew J. Rutten

IPC分类号： B24B37/10 ,  H01L21/304 ,  B24B7/00 ,  B24B17/00

CPC分类号： B24B37/105

摘要： A chemical mechanical planarization tool and method are presented employing a non-linear motion of the carrier arm relative to the polishing pad. The non-linear motion of the carrier arm relative to the polishing pad can be accomplished in a variety of ways, for example, employing a mechanical template having an irregular opening or programming the carrier displacement mechanism to move the carrier in an irregular, non-rotational X-Y path over the polishing pad.

摘要翻译： 使用载体臂相对于抛光垫的非线性运动来呈现化学机械平面化工具和方法。 载体臂相对于抛光垫的非线性运动可以以各种方式实现，例如采用具有不规则开口的机械模板或编程载体位移机构以使载体移动成不规则的非 - 抛光垫上的旋转XY路径。

公开(公告)号：US5521434A

公开(公告)日：1996-05-28

申请号：US324203

申请日：1994-10-17

申请人： John E. Cronin ,  Stephen E. Luce ,  Steven H. Voldman

发明人： John E. Cronin ,  Stephen E. Luce ,  Steven H. Voldman

IPC分类号： H01L25/00 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L23/528 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/16 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

摘要翻译： 具有通过互连和部件增强的一个或多个表面的制造方法和结果电子模块。 公开了具有例如与其侧表面成一体的电阻器和电容器的电子模块。 进一步描述了具有例如彼此电连接的互连件的电子模块，例如，侧向或侧向或端对端的表面。 此外，在此包含具有硅正面芯片的电子模块的讨论。 阐述了制造方法，所得到的电子模块和相关晶片处理的具体细节。

公开(公告)号：US5496771A

公开(公告)日：1996-03-05

申请号：US245997

申请日：1994-05-19

申请人： John E. Cronin ,  Carter W. Kaanta ,  Randy W. Mann ,  Darrell Meulemans ,  Gordon S. Starkey

发明人： John E. Cronin ,  Carter W. Kaanta ,  Randy W. Mann ,  Darrell Meulemans ,  Gordon S. Starkey

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76895 ,  H01L29/4933 ,  Y10S257/90 ,  Y10S257/903 ,  Y10S257/915

摘要： Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.

摘要翻译： 制造方法和所得的半导体结构，其中堆叠结构与局部互连材料的包络层选择性地绝缘。 制造方法包括与下面的栅极同时形成立交桥绝缘体。 具体来说，一层不可侵蚀的绝缘材料沉积在导电材料层上，大致在该区域内以构成堆叠结构。 然后执行同时蚀刻，并且所得到的绝缘体部分与下面的导电材料自对准。 绝缘体部分将堆叠与随后沉积的和平坦化的局部互连层绝缘。 进一步的处理选择包括在所选择的堆叠结构上去除硅化物形成，以及针对不同可用技术的各种平面化和蚀刻方法。 阐述制造方法和结构结构的具体细节。