公开(公告)号：US20050250318A1

公开(公告)日：2005-11-10

申请号：US11180384

申请日：2005-07-13

申请人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20060163630A1

公开(公告)日：2006-07-27

申请号：US11034597

申请日：2005-01-13

申请人： Alessandro Callegari ,  Michael Gribelyuk ,  Dianne Lacey ,  Fenton McFeely ,  Katherine Saenger ,  Sufi Zafar

发明人： Alessandro Callegari ,  Michael Gribelyuk ,  Dianne Lacey ,  Fenton McFeely ,  Katherine Saenger ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

摘要翻译： 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和反型层厚度缩小至低于Å 。

公开(公告)号：US20060151846A1

公开(公告)日：2006-07-13

申请号：US11035369

申请日：2005-01-13

申请人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

发明人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

IPC分类号： H01L29/94

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：US20060138603A1

公开(公告)日：2006-06-29

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L23/58

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US20070138578A1

公开(公告)日：2007-06-21

申请号：US11311455

申请日：2005-12-19

申请人： Alessandro Callegari ,  Michael Gribelyuk ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Sufi Zafar

发明人： Alessandro Callegari ,  Michael Gribelyuk ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 一种复合金属，其包含具有约4.75至约5.3，优选约5eV的功函数的p型金属，其在一个或多个金属上是热稳定的 提供了包括高k电介质和界面层的栅极叠层以及制造复合金属的方法。 此外，本发明的金属氧化物金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许非常有效的等效氧化物厚度（EOT）和反演 在p-金属氧化物半导体（PMOS）器件中的层厚度缩小到14埃以下。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US20050280105A1

公开(公告)日：2005-12-22

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低， 或更大。

公开(公告)号：US20050104142A1

公开(公告)日：2005-05-19

申请号：US10712575

申请日：2003-11-13

申请人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L29/76

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US06297095B1

公开(公告)日：2001-10-02

申请号：US09596399

申请日：2000-06-16

申请人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

发明人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66439 ,  H01L29/7888

摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

摘要翻译： 提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。 该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。 然后在隧道介电层（14）上生长多个纳米团簇（19）。 在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。 为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。 然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。 在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间 电极（24）。

公开(公告)号：US08409867B2

公开(公告)日：2013-04-02

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00 ,  G01N33/48

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20130005156A1

公开(公告)日：2013-01-03

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/324

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.