公开(公告)号：US10249616B2

公开(公告)日：2019-04-02

申请号：US15627835

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

公开(公告)号：US10153209B1

公开(公告)日：2018-12-11

申请号：US15888408

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L27/02 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US10008385B1

公开(公告)日：2018-06-26

申请号：US15612335

申请日：2017-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Chih-Chiang Chang ,  Mitchell Rutkowski

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/28132 ,  H01L21/76834 ,  H01L21/76897

Abstract: Methods of forming a sacrificial gate cap and a self-aligned contact for a device structure. A gate electrode is arranged between a first sidewall spacer and a second sidewall spacer. A top surface of the gate electrode is recessed to open a space above the top surface of the recessed gate electrode that partially exposes the first and second sidewall spacers. Respective sections of the first and second sidewall spacers, which are arranged above the top surface of the recessed gate electrode, are removed in order to increase a width of the space. A sacrificial cap is formed in the widened space.

公开(公告)号：US09312145B2

公开(公告)日：2016-04-12

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L21/469 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US09202697B2

公开(公告)日：2015-12-01

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying Luo ,  Feng Zhou ,  Yan Ping Shen ,  Haiting Wang ,  Haoran Shi ,  Wei Hua Tong ,  Seung Kim ,  Yong Meng Lee

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US09147572B2

公开(公告)日：2015-09-29

申请号：US13896022

申请日：2013-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Meng Luo ,  Yong Meng Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。

公开(公告)号：US09093557B2

公开(公告)日：2015-07-28

申请号：US13961318

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Haiting Wang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

Abstract translation: 通常，本发明的各方面涉及用于形成半导体器件的方法，例如具有完全中线整合的FET。 具体来说，硬掩模层和一组间隔物从栅极堆叠中移除，留下（尤其是）一组虚拟栅极。 衬套层形成在该组虚拟栅极之上并且与该组虚拟栅极相邻的源极 - 漏极区域上方。 然后将衬套层从该组虚拟栅极和源极 - 漏极区域的顶表面（或其至少一部分）移除。 然后将层间电介质（ILD）沉积在该组虚拟栅极上并在源极 - 漏极区域上方，然后去除该组虚拟栅极。 结果是可以沉积与源极 - 漏极区域的自对准接触的环境。

公开(公告)号：US20150041909A1

公开(公告)日：2015-02-12

申请号：US13961318

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Haiting Wang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

Abstract translation: 通常，本发明的各方面涉及用于形成半导体器件的方法，例如具有完全中线整合的FET。 具体来说，硬掩模层和一组间隔物从栅极堆叠中移除，留下（尤其是）一组虚拟栅极。 衬套层形成在该组虚拟栅极之上并且与该组虚拟栅极相邻的源极 - 漏极区域上方。 然后将衬套层从该组虚拟栅极和源极 - 漏极区域的顶表面（或其至少一部分）移除。 然后将层间电介质（ILD）沉积在该组虚拟栅极上并在源极 - 漏极区域上方，然后去除该组虚拟栅极。 结果是可以沉积与源极 - 漏极区域的自对准接触的环境。

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。