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    METHODS OF MANUFACTURING RF FILTERS
    15.
    发明申请
    METHODS OF MANUFACTURING RF FILTERS 审中-公开

    公开(公告)号：US20190267361A1

    公开(公告)日：2019-08-29

    申请号：US15907413

    申请日：2018-02-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Md. Sayed Kaysar Bin Rahim ,  Luke England ,  Sukeshwar Kannan

    IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L41/313 ,  H01L21/768 ,  H01L21/78 ,  H03H9/54 ,  H03H9/64 ,  H03H9/13 ,  H03H9/145 ,  H03H3/02 ,  H03H3/08

    Abstract: A product disclosed herein includes an RF filter die including an RF filter, a front side and a plurality of conductive bond pads conductively coupled to at least a portion of the RF filter, wherein at least a portion of the conductive bond pads is exposed on the front side of the RF filter die. The product also includes a TSV (Through-Substrate-Via) die that includes a plurality of conductive TSV contacts positioned on a back side of the TSV die and at least one conductive TSV (Through-Substrate-Via) structure that is conductively coupled to at least one of the plurality of conductive TSV contacts, wherein the back side of the TSV die is bonded to the front side of the RF filter such that the conductive bond pads on the RF filter die are conductively coupled to corresponding conductive TSV contacts positioned on the back side of the TSV die.

    Back biasing in SOI FET technology
    16.
    发明授权
    Back biasing in SOI FET technology 有权

    公开(公告)号：US10090227B1

    公开(公告)日：2018-10-02

    申请号：US15648602

    申请日：2017-07-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Bartlomiej Pawlak ,  Luke England

    IPC: H01L23/48 ,  H01L27/12 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/56

    Abstract: In one aspect, the present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) substrate composed of an active layer, a substrate and a buried insulating layer which is positioned on an upper surface of the substrate and below a lower surface of the active layer. At least one gate electrode having a channel region below is positioned above an upper surface of the active layer and at least one vertical connection element extends between the upper surface of the substrate and an opposite lower surface of the substrate below the at least one gate electrode. The at least one vertical connection element serves for back-biasing FETs with back-bias contacts at the rear side of the wafer.

    Interconnect structure
    19.
    发明授权
    Interconnect structure 有权

    公开(公告)号：US10381304B2

    公开(公告)日：2019-08-13

    申请号：US15664484

    申请日：2017-07-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Luke England ,  Mark W. Kuemerle

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/528

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

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