公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20180301531A1

公开(公告)日：2018-10-18

申请号：US15486351

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66742

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.

公开(公告)号：US20180138046A1

公开(公告)日：2018-05-17

申请号：US15351747

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Ruilong XIE

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/265

CPC classification number: H01L21/28123 ,  H01L21/26513 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

公开(公告)号：US20180096895A1

公开(公告)日：2018-04-05

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20180012887A1

公开(公告)日：2018-01-11

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

公开(公告)号：US20170352654A1

公开(公告)日：2017-12-07

申请号：US15170109

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Cheng CHI

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/66795

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

公开(公告)号：US20170053836A1

公开(公告)日：2017-02-23

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

Abstract translation: 一种方法包括提供具有第一和第二多个翅片的基底，其上设置有第一至少一个介电材料，去除第一介电材料的上部以暴露第一和第二多个翅片的上部，去除 第一介电材料从第二多个翅片的下部分暴露以暴露第二多个翅片的下部，在第二多个翅片的至少上部暴露部分和下部暴露部分上沉积第二至少一个电介质材料， 第一多个翅片的上暴露部分，去除第二介电材料以暴露第一和第二多个翅片的上部，并且其中第一介电材料不同于第二介电材料。 所得到的结构可以用作nFET和pFET。

公开(公告)号：US20160358826A1

公开(公告)日：2016-12-08

申请号：US14731480

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/45 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823871 ,  H01L21/283 ,  H01L21/28525 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7839 ,  H01L2221/1063

Abstract: A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

Abstract translation: 提供半导体器件中的沟槽接触外延层。 实施例包括在NFET和PFET区域中的源/漏区上形成通过层间电介质（ILD）的沟槽; 在所述ILD和所述沟槽中沉积保形氮化硅（SiN）层; 去除PFET区域中的SiN层; 在PFET区域的源极/漏极区域上生长锗（Ge）外延层; 在ILD和NFET和PFET区域的沟槽中沉积金属; 蚀刻NFET区域中的金属以暴露共形SiN层; 去除NFET区域中的SiN层; 在NFET区域的源极/漏极区域上生长III-V族外延层; 以及在ILD上和在NFET区域的沟槽中沉积金属。

公开(公告)号：US20160315182A1

公开(公告)日：2016-10-27

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160181384A1

公开(公告)日：2016-06-23

申请号：US14581741

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen YEH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。